公开(公告)号：US20240031121A1

公开(公告)日：2024-01-25

申请号：US17871937

申请日：2022-07-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Arnon Sattinger ,  Natan Manevich ,  Wojciech Wasko ,  Ariel Almog ,  Bar Or Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.

公开(公告)号：US20230362084A1

公开(公告)日：2023-11-09

申请号：US18106933

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Alex Vainman ,  Roee Moyal

IPC: H04L43/0888

CPC classification number: H04L43/0888

Abstract: A system includes a device configured to execute workloads coupled to a processing device. The processing device is to receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. The processing device is further to determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values. The processing device is to execute the one or more workloads at the determined rate.

公开(公告)号：US20230361900A1

公开(公告)日：2023-11-09

申请号：US18107442

申请日：2023-02-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: H04J3/06 ,  H04L47/25

CPC classification number: H04J3/0652 ,  H04L47/25 ,  H04J3/0667

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.

公开(公告)号：US11757614B2

公开(公告)日：2023-09-12

申请号：US17315396

申请日：2021-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Teferet Geula ,  Amit Mandelbaum ,  Ariel Almog

IPC: H04L7/00 ,  G06N20/00 ,  H04L43/106

CPC classification number: H04L7/0054 ,  G06N20/00 ,  H04L43/106

Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.

公开(公告)号：US11711210B2

公开(公告)日：2023-07-25

申请号：US17227321

申请日：2021-04-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Syrivelis ,  Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Elad Mentovich ,  Dotan David Levi

IPC: H04L9/08 ,  H04L9/40 ,  G06N10/00 ,  G06F12/14

CPC classification number: H04L9/0858 ,  G06F12/1408 ,  G06N10/00 ,  H04L63/061 ,  G06F2212/1052

Abstract: In one embodiment, a secure computing system comprises a key generation sub-system configured to generate cryptographic keys and corresponding key labels for distribution to computer clusters, each computer cluster including a plurality of respective endpoints, a plurality of quantum key distribution (QKD) devices connected via respective optical fiber connections, and configured to securely distribute the generated cryptographic keys among the computer clusters, and a key orchestration sub-system configured to manage caching of the cryptographic keys in advance of receiving key requests from applications running on ones of the endpoints, and provide respective ones of the cryptographic keys to the applications to enable secure communication among the applications.

公开(公告)号：US20230231695A1

公开(公告)日：2023-07-20

申请号：US17579630

申请日：2022-01-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

公开(公告)号：US11543852B2

公开(公告)日：2023-01-03

申请号：US16779611

申请日：2020-02-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Liron Mula ,  Ariel Almog ,  Aviad Raveh ,  Yuval Itkin

IPC: G06F1/12 ,  H03C3/09

Abstract: In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.

公开(公告)号：US20220357763A1

公开(公告)日：2022-11-10

申请号：US17313026

申请日：2021-05-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Itai Levy ,  Dotan David Levi ,  Nir Nitzani ,  Natan Manevich ,  Alex Vaynman ,  Ariel Almog

IPC: G06F1/12 ,  H04L7/00 ,  G06F13/20

Abstract: A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.

公开(公告)号：US20220224500A1

公开(公告)日：2022-07-14

申请号：US17148605

申请日：2021-01-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

IPC: H04L7/00

Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

公开(公告)号：US11283454B2

公开(公告)日：2022-03-22

申请号：US16920772

申请日：2020-07-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.