公开(公告)号：US20220012592A1

公开(公告)日：2022-01-13

申请号：US17483693

申请日：2021-09-23

申请人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

发明人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

IPC分类号： G06N3/08 ,  H03M7/30 ,  G06F17/16

摘要： Methods, apparatus, systems, and articles of manufacture to perform weight and activation compression and decompression are disclosed. An example apparatus includes memory, instructions in the apparatus, and processor circuitry to execute the instructions to execute a compression operation to obtain compressed data corresponding to weights in a weight matrix, and determine meta-data associated with the weight matrix, a first portion of the meta-data indicative of whether the weight matrix is compressed, a second portion of the meta-data indicative of a cache size of the compressed data, and a third portion of the meta-data indicative of the compression operation executed to obtain the compressed data.

公开(公告)号：US20170177429A1

公开(公告)日：2017-06-22

申请号：US14977354

申请日：2015-12-21

申请人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20160283232A1

公开(公告)日：2016-09-29

申请号：US14671569

申请日：2015-03-27

申请人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

发明人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/46

摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.

摘要翻译： 处理器包括核心和预取器。 预取器包括发出对包括请求的预取的数据的请求的逻辑。 核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

公开(公告)号：US20150089280A1

公开(公告)日：2015-03-26

申请号：US14038334

申请日：2013-09-26

申请人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

发明人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

摘要翻译： 提供了同时处理多个数据错误的机制。 处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。 如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。 如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

公开(公告)号：US20140122811A1

公开(公告)日：2014-05-01

申请号：US13664682

申请日：2012-10-31

申请人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

发明人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC分类号： G06F12/08

CPC分类号： G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US08688917B2

公开(公告)日：2014-04-01

申请号：US13355302

申请日：2012-01-20

申请人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

发明人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/084

摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

公开(公告)号：US08516577B2

公开(公告)日：2013-08-20

申请号：US12887898

申请日：2010-09-22

申请人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

发明人： Michael S. Bair ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC分类号： G06F21/00

CPC分类号： G06F9/526

摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US09411728B2

公开(公告)日：2016-08-09

申请号：US13994399

申请日：2011-12-23

申请人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

发明人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

IPC分类号： G06F13/00 ,  G06F12/08 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

摘要翻译： 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

公开(公告)号：US20160124802A1

公开(公告)日：2016-05-05

申请号：US14531498

申请日：2014-11-03

申请人： Ron Gabor ,  Raanan Sade ,  Joseph Nuzman

发明人： Ron Gabor ,  Raanan Sade ,  Joseph Nuzman

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC分类号： G06F11/10

摘要： Systems and methods for memory corruption detection. An example processing system comprises a processing core including a register to store a base address of a memory corruption detection (MCD) table. The processing core is configured to validate a pointer referenced by a memory access instruction, by comparing a first value derived from a first portion of the pointer to a second value stored in the MCD table at an offset referenced by a second portion of the pointer.

摘要翻译： 内存损坏检测的系统和方法 示例性处理系统包括处理核心，其包括用于存储存储器破坏检测（MCD）表的基址的寄存器。 处理核心被配置为通过将由指针的第一部分导出的第一值与由指针的第二部分引用的偏移量相对应地存储在MCD表中的第二值进行比较来验证由存储器访问指令引用的指针。

公开(公告)号：US20130326145A1

公开(公告)日：2013-12-05

申请号：US13994399

申请日：2011-12-23

申请人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

发明人： Ron Shalev ,  Yiftach Gilad ,  Shlomo Raikin ,  Igor Yanover ,  Stanislav Shwartsman ,  Raanan Sade

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

摘要翻译： 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态和与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。