公开(公告)号：US20160283232A1

公开(公告)日：2016-09-29

申请号：US14671569

申请日：2015-03-27

申请人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

发明人： Raanan Sade ,  Ryan L. Carlson ,  Larisa Novakovsky ,  Erik G. Hallnor ,  Ravi Rajwar ,  Roman Dementiev

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/46

摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.

摘要翻译： 处理器包括核心和预取器。 预取器包括发出对包括请求的预取的数据的请求的逻辑。 核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

公开(公告)号：US09990287B2

公开(公告)日：2018-06-05

申请号：US13994122

申请日：2011-12-21

申请人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

发明人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

IPC分类号： G06F13/38 ,  G06T1/20 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F13/16 ,  G06T1/60 ,  G09G5/00 ,  G06F12/0866

CPC分类号： G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3881 ,  G06F12/0866 ,  G06F13/1673 ,  G06F13/38 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006

摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

公开(公告)号：US20140192069A1

公开(公告)日：2014-07-10

申请号：US13994122

申请日：2011-12-21

申请人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

发明人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

IPC分类号： G06F13/38 ,  G06F13/16 ,  G06T1/60 ,  G06F12/08 ,  G06T1/20

CPC分类号： G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3881 ,  G06F12/0866 ,  G06F13/1673 ,  G06F13/38 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006

摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

摘要翻译： 描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。 例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

公开(公告)号：US20140208031A1

公开(公告)日：2014-07-24

申请号：US13994724

申请日：2011-12-21

申请人： Shlomo Raikin ,  Robert Valentine ,  Raanan Sade ,  Julius Yuli Mandelbalt ,  Ron Shalev ,  Larisa Novakovsky

发明人： Shlomo Raikin ,  Robert Valentine ,  Raanan Sade ,  Julius Yuli Mandelbalt ,  Ron Shalev ,  Larisa Novakovsky

IPC分类号： G06F12/08 ,  G06T1/60

CPC分类号： G06F12/0811 ,  G06F9/3828 ,  G06F9/3891 ,  G06F12/0891 ,  G06T1/60

摘要： An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

摘要翻译： 描述了一种用于在中央处理单元（CPU）内有效地将数据从生产者核心传送到消费者核心的装置和方法。 例如，一种方法的一个实施例包括：一种用于将数据块从中央处理单元（CPU）的生产者核心转移到CPU的消费者核心的方法，包括：将数据写入到所述CPU的生产者核心内的缓冲器 CPU直到指定数据量被写入; 在检测到指定量的数据被写入时，响应地产生驱逐周期，使得将数据从填充缓冲器传送到可由生产者核心和消费者核心访问的高速缓存的逐出循环; 并且在消费者核心检测到数据在高速缓存中可用时，在从消费者核心接收到读取信号时从高速缓存提供数据给消费者核心。

公开(公告)号：US20140122811A1

公开(公告)日：2014-05-01

申请号：US13664682

申请日：2012-10-31

申请人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

发明人： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC分类号： G06F12/08

CPC分类号： G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

摘要翻译： 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US09448879B2

公开(公告)日：2016-09-20

申请号：US13994105

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

发明人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07

CPC分类号： G06F11/1064 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1407

摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

摘要翻译： 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

公开(公告)号：US20160092357A1

公开(公告)日：2016-03-31

申请号：US14497549

申请日：2014-09-26

申请人： Shani Rehana ,  Alexander Gendler ,  Larisa Novakovsky

发明人： Shani Rehana ,  Alexander Gendler ,  Larisa Novakovsky

IPC分类号： G06F12/08

CPC分类号： G06F1/26 ,  G06F1/12 ,  G06F3/0656 ,  G06F5/10 ,  G06F15/17331

摘要： In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括根据第一时钟进行操作的第一域。 第一域包括首先在先出缓冲器（有效载荷BGF）中存储数据分组的写入源，有效负载气泡生成器，以及写入信用逻辑以维持写入信用的计数。 处理器还包括第二域，以便按照第二时钟进行操作。 当写入源具有在第二时钟关闭时要存储的数据包时，写入源将数据包写入有效载荷BGF，响应于至少一个写入信用的计数，并且在第二个时钟为 重新启动第二个域是从有效载荷BGF读取数据包。 描述和要求保护其他实施例。

公开(公告)号：US20190005160A1

公开(公告)日：2019-01-03

申请号：US15640532

申请日：2017-07-01

申请人： Tsvika Kurts ,  Alexander Gendler ,  Larisa Novakovsky ,  Anwar Azaarura Zaa'Rura ,  Afik Sela ,  Genadi Kazakevich ,  Alexandra Shainshein ,  Ariel Sabba

发明人： Tsvika Kurts ,  Alexander Gendler ,  Larisa Novakovsky ,  Anwar Azaarura Zaa'Rura ,  Afik Sela ,  Genadi Kazakevich ,  Alexandra Shainshein ,  Ariel Sabba

IPC分类号： G06F17/50 ,  G01R31/317

摘要： An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

公开(公告)号：US20070157208A1

公开(公告)日：2007-07-05

申请号：US11321643

申请日：2005-12-30

申请人： Abraham Mendelson ,  Julius Mandelblat ,  Larisa Novakovsky

发明人： Abraham Mendelson ,  Julius Mandelblat ,  Larisa Novakovsky

IPC分类号： G06F9/46

CPC分类号： G06F9/5011 ,  G06F2209/507

摘要： Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

摘要翻译： 本发明的实施例提供了一种资源管理机制，用于监视资源的可用性，检测拒绝的原因，区分不同类型的拒绝，并相应地管理不同的类型。 例如，根据本发明的实施例的队列管理器可以能够基于拒绝的原因将拒绝的请求例如分类为“长拒绝”或“短拒”，并且时间量 排除条件预计将保持有效。 短拒绝请求可以重新安排在适当的服务队列中，而长的拒绝请求可能被暂停在拒绝队列中。 描述和要求保护其他特征。

公开(公告)号：US20150178202A1

公开(公告)日：2015-06-25

申请号：US14137432

申请日：2013-12-20

申请人： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

发明人： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

摘要： An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

摘要翻译： 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。