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公开(公告)号：US06746822B1
公开(公告)日：2004-06-08
申请号：US10050484
申请日：2002-01-16
IPC分类号： G03F720
CPC分类号： G03F7/265 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： Disclosed are methods of processing a semiconductor structure, involving the steps of depositing a light-degradable surface coupling agent on a semiconductor substrate; depositing a resist over the light-degradable surface coupling agent; irradiating portions of the resist, wherein the light-degradable surface coupling agent under the irradiated portions of the resist at least partially decomposes; and developing the resist.
摘要翻译： 公开了处理半导体结构的方法，包括在半导体衬底上沉积可光降解的表面偶联剂的步骤; 在光可降解表面偶联剂上沉积抗蚀剂; 照射抗蚀剂的部分，其中抗蚀剂照射部分下的可光降解表面偶联剂至少部分分解; 并开发抗蚀剂。
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公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译： 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以调节晶片各部分的温度。
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13.发明授权Reducing resist residue defects in open area on patterned wafer using trim mask 有权使用修剪掩模减少图案化晶片上的开放区域中的抗蚀剂残留缺陷公开(公告)号：US06613500B1
公开(公告)日：2003-09-02
申请号：US09824079
申请日：2001-04-02
IPC分类号： G03F700
CPC分类号： G03F7/70425 , G03F7/2022 , G03F7/203 , G03F7/70466
摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.
摘要翻译： 本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。 该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。
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公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译： 本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。 本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。 与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。 散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。 也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。
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15.发明授权System and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay 有权用于通过减轻掩模旋转对覆盖层的影响来促进晶片对准的系统和方法公开(公告)号：US06552790B1
公开(公告)日：2003-04-22
申请号：US09788905
申请日：2001-02-20
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G03F9/7003 , G03F9/7076 , G03F9/7084
摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design, and a first and second set of scribe marks. The first and second sets of scribe marks have an associated symmetry relative to the reticle design. The design and scribe marks are printed at selected field locations on a surface layer of the wafer. The first and second sets of scribe marks as printed at adjacent fields on the surface layer of wafer form a composite set of scribe marks. The symmetric relationship between the first and second sets of scribe marks results in the composite set of scribe marks substantially negating print errors of the marks due to reticle rotation and/or lens magnification with respect to a geometric reference point of the composite set of scribe marks. The employment of the composite set of scribe marks, such as to locate a corresponding virtual alignment mark, substantially facilitates mitigation of overlay error in wafer alignment.
摘要翻译： 本发明涉及晶圆对准。 使用掩模版，其包括设计，以及第一和第二组划线标记。 第一组和第二组划痕具有相对于标线设计的相关对称性。 设计和划痕被印在晶片的表面层上的选定的场地。 在晶片表面层上的相邻场印刷的第一组和第二组刻痕形成一组复合的划线标记。 第一组和第二组划线标记之间的对称关系导致划线标记的复合组合基本上抵消了由于标线转动和/或透镜倍率而导致的标记的印刷误差相对于复合组划线标记的几何参考点 。 使用复合组划线标记，例如定位相应的虚拟对准标记，基本上有助于减轻晶片对准中的重叠误差。
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公开(公告)号：US06524944B1
公开(公告)日：2003-02-25
申请号：US09617374
申请日：2000-07-17
IPC分类号： H01L214763
CPC分类号： H01L21/7682
摘要： One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less. Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底上的金属线之间形成高级低k材料的方法，包括提供其上具有多条金属线的半导体衬底的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 以及加热或蚀刻半导体衬底中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括金属线之间的至少一个空气空隙的高级低k材料，先进的低k材料具有 介电常数约为2或更小。 本发明的另一方面涉及一种形成半导体结构的方法，包括在半导体结构上形成第一多个金属线的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 在所述旋涂材料中形成暴露金属线的一部分并沉积金属以在所述开口中形成多个金属通孔的多个开口; 在所述金属通孔的至少一部分上形成第二多个金属线; 以及加热或蚀刻半导体结构中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括至少一个空气空隙的先进的低k材料，该介电常数为约 2以下。
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公开(公告)号：US06444381B1
公开(公告)日：2002-09-03
申请号：US09729295
申请日：2000-12-04
申请人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
发明人： Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Sanjay K. Yedur
IPC分类号： G03F900
CPC分类号： G03F1/74 , Y10S430/143
摘要： One aspect of the present invention relates to a method for reducing carbon contamination on a mask involving placing a mask plate having carbon-containing contaminants thereon in a processing chamber; simultaneously contacting the mask plate with oxygen and exposing the mask plate with a flood exposure of electron beams wherein the carbon-containing contaminants are converted to a by-product; and removing the by-product from the processing chamber.
摘要翻译： 本发明的一个方面涉及一种用于减少掩模上的碳污染的方法，其涉及将具有含碳污染物的掩模板放置在处理室中; 同时使掩模板与氧气接触，并将电子束的暴露暴露于掩模板，其中含碳污染物转化为副产物; 并从处理室中除去副产物。
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公开(公告)号：US06423650B1
公开(公告)日：2002-07-23
申请号：US09371715
申请日：1999-08-09
IPC分类号： H01L2131
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.
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公开(公告)号：US06335152B1
公开(公告)日：2002-01-01
申请号：US09564408
申请日：2000-05-01
IPC分类号： G03F738
CPC分类号： G03F7/38
摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.
摘要翻译： 在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。
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20.发明授权公开(公告)号：US06291137B1
公开(公告)日：2001-09-18
申请号：US09234380
申请日：1999-01-20
IPC分类号： G03C500
CPC分类号： H01L21/76885 , H01L21/28132 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化侧壁模板，其中所述导电膜的第二部分被暴露，所述侧壁模板在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述侧壁模板上沉积侧壁膜，所述侧壁膜具有邻近所述侧壁模板的侧壁的垂直部分和在不邻近所述侧壁模板的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的侧壁模板; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。
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