公开(公告)号：US09606064B2

公开(公告)日：2017-03-28

申请号：US14380738

申请日：2012-02-27

申请人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

发明人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

IPC分类号： G01N21/66 ,  G01R15/24 ,  G01R31/311

CPC分类号： G01N21/66 ,  G01R15/24 ,  G01R31/311

摘要： A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

公开(公告)号：US09431338B2

公开(公告)日：2016-08-30

申请号：US13509922

申请日：2009-11-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G11C11/24 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/495 ,  G11C29/50 ,  H01L21/66

CPC分类号： H01L23/5223 ,  G11C2029/5002 ,  H01L22/14 ,  H01L22/22 ,  H01L23/49589 ,  H01L23/5286 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

摘要翻译： 用于集成电路（IC）的旁路电容器电路包括一个或多个电容性器件，每个电容器件布置在包括IC的管芯的密封环区域的段中。 提供用于IC的旁路电容的方法包括提供包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置一个或多个电容性装置; 切割半导体晶片器件; 在测试模式中，对于所述一个或多个电容性装置中的每一个，启用所述电容性装置，确定指示所述电容性装置的可操作性的可操作性参数值，以及将所述可操作性参数存储在存储装置中; 并且在正常操作模式中，根据具有指示对应的电容性器件的非缺陷性的相关联的可操作性参数值的一个或多个电容器件的电容，向IC提供旁路电容。

公开(公告)号：US20150098540A1

公开(公告)日：2015-04-09

申请号：US14373924

申请日：2012-02-24

申请人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

发明人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

IPC分类号： H04L25/45 ,  H04L25/44

CPC分类号： H04L25/45 ,  G06F1/10 ,  H04L25/44

摘要： A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

摘要翻译： 描述了用于数字同步系统的时钟分配模块。 所述时钟分配模块包括被布置为包括相对于参考时钟信号的传播延迟的时钟信号的第一节点，至少一个另外的节点，被布置为包括时钟信号，该时钟信号包括相对于参考时钟信号的参考时钟信号的传播延迟 第一个节点和一个时钟配置模块。 时钟配置模块被布置成接收时钟分配模块的第一节点和至少一个另外节点之间的时钟偏移的至少一个指示，并且至少部分地基于第一节点选择性地将第一节点耦合到至少一个另外的节点 其间的时钟偏移的至少一个指示。

公开(公告)号：US20140021557A1

公开(公告)日：2014-01-23

申请号：US14008581

申请日：2011-03-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen ,  Dov Tzytkin

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen ,  Dov Tzytkin

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/0928

摘要： There is provided a semiconductor Integrated Circuit device having forward well biasing, in which at least one protection device is connected between a supply voltage and a forward well bias voltage.

摘要翻译： 提供了具有正向井偏压的半导体集成电路装置，其中至少一个保护装置连接在电源电压和正向阱偏置电压之间。

公开(公告)号：US20130076421A1

公开(公告)日：2013-03-28

申请号：US13634730

申请日：2010-06-11

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： H03K3/00

CPC分类号： H03K3/00 ,  H03K3/012 ,  H03K19/0008

摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.

摘要翻译： 一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

公开(公告)号：US08228080B2

公开(公告)日：2012-07-24

申请号：US12509279

申请日：2009-07-24

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G01R31/02 ,  G05F3/02 ,  H01L23/58 ,  G06F1/26

CPC分类号： G01R19/0092

摘要： A device and a method for estimating a current; the method includes: setting an impedance of a power gating circuit to a measurement value; wherein the power gating circuit selectively provides power to a circuit of an integrated circuit; measuring, during a measurement period, an electrical parameter indicative of a current that flows through the power gating circuit; and reducing an impedance of the power gating circuit to a power provision value to reduce a voltage developed on the power gating circuit during a power provision period.

摘要翻译： 一种用于估计电流的装置和方法; 该方法包括：将电源门控电路的阻抗设置为测量值; 其中所述功率门控电路选择性地向集成电路的电路提供电力; 在测量周期期间测量指示流过所述电力门控电路的电流的电参数; 并且将功率门控电路的阻抗减小到功率供应值以减小在供电周期期间在功率选通电路上产生的电压。

公开(公告)号：US07941721B2

公开(公告)日：2011-05-10

申请号：US12550516

申请日：2009-08-31

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： G06F11/00

CPC分类号： G01R31/318538 ,  G01R31/318541

摘要： A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan register, at a second frequency and in a parallel manner, to a target boundary scan register; wherein the second frequency is higher than the first frequency; reading the content of the target boundary scan register; wherein the source and target boundary scan registers are selected from a first boundary scan register of the first device and a second boundary scan register of the second device; and evaluating a connectivity between the first and second device in response to a relationship between the first test word and the content of the target boundary scan register.

摘要翻译： 一种用于测试第一设备和第二设备之间的连接性的设备和方法，所述方法包括：以第一频率和串行方式将第一测试字写入源边界扫描寄存器; 将源边界扫描寄存器的内容以第二频率和并行方式写入目标边界扫描寄存器; 其中所述第二频率高于所述第一频率; 读取目标边界扫描寄存器的内容; 其中所述源和目标边界扫描寄存器从所述第一设备的第一边界扫描寄存器和所述第二设备的第二边界扫描寄存器中选择; 以及响应于所述第一测试字与所述目标边界扫描寄存器的内容之间的关系来评估所述第一和第二设备之间的连接性。

公开(公告)号：US09500679B2

公开(公告)日：2016-11-22

申请号：US14415151

申请日：2012-07-19

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G01F15/06 ,  G01R19/10 ,  G01R31/28

CPC分类号： G01R19/10 ,  G01R31/2856

摘要： A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

公开(公告)号：US09178730B2

公开(公告)日：2015-11-03

申请号：US14373924

申请日：2012-02-24

申请人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

发明人： Michael Priel ,  David Dzebisashvili ,  Leonid Fleshel

IPC分类号： H04L7/00 ,  H04L25/45 ,  G06F1/10 ,  H04L25/44

CPC分类号： H04L25/45 ,  G06F1/10 ,  H04L25/44

摘要： A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

摘要翻译： 描述了用于数字同步系统的时钟分配模块。 所述时钟分配模块包括被布置为包括相对于参考时钟信号的传播延迟的时钟信号的第一节点，至少一个另外的节点，被布置为包括时钟信号，该时钟信号包括相对于参考时钟信号的参考时钟信号的传播延迟 第一个节点和一个时钟配置模块。 时钟配置模块被布置成接收时钟分配模块的第一节点和至少一个另外节点之间的时钟偏移的至少一个指示，并且至少部分地基于第一节点选择性地将第一节点耦合到至少一个另外的节点 其间的时钟偏移的至少一个指示。

公开(公告)号：US20150091607A1

公开(公告)日：2015-04-02

申请号：US14398868

申请日：2012-05-30

申请人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

发明人： Michael Priel ,  Leonid Fleshel ,  Anton Rozen

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/173

CPC分类号： H03K19/0016 ,  H03K5/135 ,  H03K19/00323 ,  H03K19/00369 ,  H03K19/173

摘要： A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.

摘要翻译： 一种顺序逻辑电路，包括：第一锁存器组件，包括布置成接收输入信号的数据输入;布置成输出第一锁存器组件的当前逻辑状态的数据输出;以及布置成接收时钟信号的时钟输入; 所述第一锁存部件被布置为在接收到的所述时钟信号时包括透明状态，由此包括第一逻辑状态，并且包括在接收到的所述时钟信号的锁存状态，由此包括第二逻辑状态，以及包括数据输入的第二锁存部件 布置成接收输入信号，数据输出可操作地耦合到顺序逻辑电路的输出并且被布置成输出第二锁存部件的当前状态和布置成接收时钟信号的时钟输入; 所述第二锁存器组件被布置为在接收到的所述时钟信号后包括透明状态，由此包括第二逻辑状态，并且包括在接收到的所述时钟信号时的锁存状态，由此包括第一逻辑状态。 顺序逻辑电路被布置为在至少第一操作模式中操作，其中第一锁存部件的数据输入和第二锁存部件的数据输入可操作地耦合到顺序逻辑电路的第一输入，并且其中 提供给第一和第二锁存部件的时钟信号使得第二锁存部件从透明状态到锁存状态的转变相对于第一锁存部件从透明状态到锁存状态的相应转变而延迟， 接收延迟数据的时间段。