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公开(公告)号：US09553178B2
公开(公告)日：2017-01-24
申请号：US12977755
申请日：2010-12-23
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/4236
摘要： A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material.
摘要翻译： 半导体部件包括第一导电类型的第一发射极区域，第二导电类型的第二发射极区域，布置在第一和第二发射极区域之间的第一基极区域和第一控制结构。 第一控制结构包括布置在第一发射区附近的控制电极，控制电极通过第一介电层与第一发射区绝缘，并沿着半导体部件的电流流动方向延伸。 第一控制结构包括第一控制连接和布置在第一控制连接和控制电极之间并且包括半导体材料的至少一个第一连接区域。
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12.发明申请Method for Forming a Semiconductor Device, and a Semiconductor with an Integrated Poly-Diode 有权用于形成半导体器件的方法和具有集成多极二极管的半导体公开(公告)号：US20120049270A1
公开(公告)日：2012-03-01
申请号：US12871038
申请日：2010-08-30
IPC分类号： H01L29/78 , H01L21/336 , H01L21/329
CPC分类号： H01L29/66143 , H01L21/823487 , H01L29/0626 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/6609 , H01L29/6634 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7813
摘要： A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.
摘要翻译： 提供了一种用于形成场效应功率半导体的方法。 该方法包括提供半导体本体，邻近半导体主体的主表面布置的导电区域和布置在主水平表面上的绝缘层。 通过绝缘层蚀刻窄沟槽以暴露导电区域。 沉积多晶半导体层并形成垂直多晶二极管结构。 多晶半导体层的最小垂直厚度为窄沟槽的最大水平延伸的至少一半。 通过多晶半导体层的无掩模背面蚀刻，在窄沟槽中形成形成垂直多晶二极管结构的至少一部分的多晶区域。 此外，提供了具有沟槽多晶二极管的半导体器件。
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公开(公告)号：US20110156095A1
公开(公告)日：2011-06-30
申请号：US12977755
申请日：2010-12-23
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/4236
摘要： A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material.
摘要翻译： 半导体部件包括第一导电类型的第一发射极区域，第二导电类型的第二发射极区域，布置在第一和第二发射极区域之间的第一基极区域和第一控制结构。 第一控制结构包括布置在第一发射区附近的控制电极，控制电极通过第一介电层与第一发射区绝缘，并沿着半导体部件的电流流动方向延伸。 第一控制结构包括第一控制连接和布置在第一控制连接和控制电极之间并且包括半导体材料的至少一个第一连接区域。
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公开(公告)号：US20130264607A1
公开(公告)日：2013-10-10
申请号：US13441364
申请日：2012-04-06
申请人： Dorothea Werber , Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze , Franz Hirler , Alexander Philippou
发明人： Dorothea Werber , Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze , Franz Hirler , Alexander Philippou
IPC分类号： H01L29/739
CPC分类号： H01L29/7396 , H01L29/0696 , H01L29/0834
摘要： A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side.
摘要翻译： 半导体包括布置在半导体主体的第一侧和第二侧之间的第一导电类型的漂移区。 半导体器件还包括第一导电类型的第一区域和沿着平行于第二侧面的第一方向布置的第二导电类型的第二区域。 半导体器件还包括邻近第一和第二区域的第二侧的电极。 半导体器件还包括布置在漂移区和第一区之间的第二导电类型的第三区。 第三区域与第二区域和第二区域隔开。
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15.发明授权Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode 有权用于形成半导体器件的方法和具有集成多极二极管的半导体公开(公告)号：US08435853B2
公开(公告)日：2013-05-07
申请号：US12871038
申请日：2010-08-30
IPC分类号： H01L21/8234
CPC分类号： H01L29/66143 , H01L21/823487 , H01L29/0626 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/6609 , H01L29/6634 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7813
摘要： A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.
摘要翻译： 提供了一种用于形成场效应功率半导体的方法。 该方法包括提供半导体本体，邻近半导体主体的主表面布置的导电区域和布置在主水平表面上的绝缘层。 通过绝缘层蚀刻窄沟槽以暴露导电区域。 沉积多晶半导体层并形成垂直多晶二极管结构。 多晶半导体层的最小垂直厚度为窄沟槽的最大水平延伸的至少一半。 通过多晶半导体层的无掩模背面蚀刻，在窄沟槽中形成形成垂直多晶二极管结构的至少一部分的多晶区域。 此外，提供了具有沟槽多晶二极管的半导体器件。
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公开(公告)号：US09018674B2
公开(公告)日：2015-04-28
申请号：US13441364
申请日：2012-04-06
申请人： Dorothea Werber , Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze , Franz Hirler , Alexander Philippou
发明人： Dorothea Werber , Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze , Franz Hirler , Alexander Philippou
IPC分类号： H01L29/739 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7396 , H01L29/0696 , H01L29/0834
摘要： A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side.
摘要翻译： 半导体包括布置在半导体主体的第一侧和第二侧之间的第一导电类型的漂移区。 半导体器件还包括第一导电类型的第一区域和沿着平行于第二侧面的第一方向布置的第二导电类型的第二区域。 半导体器件还包括邻近第一和第二区域的第二侧的电极。 半导体器件还包括布置在漂移区和第一区之间的第二导电类型的第三区。 第三区域与第二区域和第二区域隔开。
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公开(公告)号：US08564098B2
公开(公告)日：2013-10-22
申请号：US12718381
申请日：2010-03-05
IPC分类号： H01L21/02
CPC分类号： H01L29/739 , H03K17/0412
摘要： Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component.
摘要翻译： 公开了一种用于控制双极半导体部件和双极型半导体部件的基极区域中的复合率的方法。
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18.发明申请SEMICONDUCTOR COMPONENT INCLUDING A MONOCRYSTALLINE SEMICONDUCTOR BODY AND METHOD 审中-公开包含单晶半导体器件和方法的半导体元件公开(公告)号：US20080246055A1
公开(公告)日：2008-10-09
申请号：US11867411
申请日：2007-10-04
IPC分类号： H01L29/739 , H01L29/78 , H01L21/331
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/16 , H01L29/402 , H01L29/41766 , H01L29/66128 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/7397 , H01L29/861 , H01L29/8611
摘要： A semiconductor component comprising a monocrystalline semiconductor body, and to a method for producing the same is disclosed. In one embodiment, the semiconductor body has a semiconductor component structure with regions of a porous-mono crystalline semiconductor.
摘要翻译： 公开了一种包括单晶半导体本体的半导体元件及其制造方法。 在一个实施例中，半导体本体具有具有多孔 - 单晶半导体区域的半导体部件结构。
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公开(公告)号：US08829584B2
公开(公告)日：2014-09-09
申请号：US13614479
申请日：2012-09-13
IPC分类号： H01L27/07
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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公开(公告)号：US08273622B2
公开(公告)日：2012-09-25
申请号：US13161050
申请日：2011-06-15
IPC分类号： H01L29/94
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译： 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。
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