公开(公告)号：US11557608B2

公开(公告)日：2023-01-17

申请号：US17393664

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20200373325A1

公开(公告)日：2020-11-26

申请号：US16988548

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/08 ,  H01L21/02

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11289501B2

公开(公告)日：2022-03-29

申请号：US16417162

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220037357A1

公开(公告)日：2022-02-03

申请号：US17501951

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11171153B2

公开(公告)日：2021-11-09

申请号：US16681200

申请日：2019-11-12

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210327898A1

公开(公告)日：2021-10-21

申请号：US17328237

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  G11C16/08 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11081497B2

公开(公告)日：2021-08-03

申请号：US16547885

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20200373322A1

公开(公告)日：2020-11-26

申请号：US16417162

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10777576B1

公开(公告)日：2020-09-15

申请号：US16374527

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L21/02 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/08

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240268116A1

公开(公告)日：2024-08-08

申请号：US18403266

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Kranthi Kumar Vaidyula ,  Davide Resnati ,  Byeung Chul Kim ,  Kyubong Jung ,  Jameer Babasaheb Mulani ,  Jae Kyu Choi ,  Gianpietro Carnevale

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. Channel openings are formed through the first and second tiers. Charge-storage material is formed in the channel openings through the first and second tiers. The charge-storage material comprises a first charge-trap density. The first charge-trap density of the charge-storage material that is in the first tiers is increased as compared to the charge-storage material that is in the second tiers to a second charge-trap density. Channel material is formed in the channel openings through the first and second tiers and that is laterally-inward of the charge-storage material. Other embodiment, including structure, are disclosed.