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公开(公告)号：US11955160B2
公开(公告)日：2024-04-09
申请号：US17846967
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Kevin G. Werhane , Jason M. Johnson , Daniel S. Miller
IPC: H03K5/133 , G11C11/4076 , G11C29/54
CPC classification number: G11C11/4076 , G11C29/54 , H03K5/133
Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
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公开(公告)号：US20240021262A1
公开(公告)日：2024-01-18
申请号：US18137388
申请日：2023-04-20
Applicant: Micron Technology, Inc.
Inventor： Takuya Tamano , Yoshinori Fujiwara , Daniel S. Miller
CPC classification number: G11C29/46 , G11C29/4401
Abstract: Methods, apparatuses, and systems related to adjustment of circuit tests are described. A memory device may include a self-test circuit that is configured to selectively suspend collection and/or processing of test results for one or more portions of the self-test.
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公开(公告)号：US20230069351A1
公开(公告)日：2023-03-02
申请号：US17411206
申请日：2021-08-25
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Daniel S. Miller
Abstract: An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.
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公开(公告)号：US20230063588A1
公开(公告)日：2023-03-02
申请号：US17464650
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Daniel S. Miller
Abstract: Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.
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公开(公告)号：US10923172B2
公开(公告)日：2021-02-16
申请号：US16812854
申请日：2020-03-09
Applicant: Micron Technology, Inc.
IPC: G11C11/406 , G11C5/14 , G11C11/4091 , G11C8/10 , G11C11/4074
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.
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Patent Agency Ranking
公开(公告)号：US10593392B1
公开(公告)日：2020-03-17
申请号：US16226525
申请日：2018-12-19
Applicant: Micron Technology, Inc.
IPC: G11C11/40 , G11C11/406 , G11C5/14 , G11C11/4091 , G11C8/10 , G11C11/4074
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.
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公开(公告)号：US20240071560A1
公开(公告)日：2024-02-29
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US11170837B1
公开(公告)日：2021-11-09
申请号：US16860498
申请日：2020-04-28
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Yoshinori Fujiwara
IPC: G11C11/22 , G11C11/4096 , G11C29/04 , G11C11/4094
Abstract: Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
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公开(公告)号：US20210335410A1
公开(公告)日：2021-10-28
申请号：US16860498
申请日：2020-04-28
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Yoshinori Fujiwara
IPC: G11C11/22 , G11C11/4096 , G11C11/4094 , G11C29/04
Abstract: Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
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公开(公告)号：US11081166B1
公开(公告)日：2021-08-03
申请号：US17000202
申请日：2020-08-21
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Jason M. Johnson , Yoshinori Fujiwara , Tyrel Z. Jensen , Daniel S. Miller , David E. Jefferson , Vivek Kotti
IPC: G11C11/408 , G11C11/22
Abstract: Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
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