公开(公告)号：US11797186B2

公开(公告)日：2023-10-24

申请号：US16951299

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

公开(公告)号：US20220404985A1

公开(公告)日：2022-12-22

申请号：US17863994

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

公开(公告)号：US10936221B2

公开(公告)日：2021-03-02

申请号：US15981708

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  James Brian Johnson

IPC: G11C7/10 ,  G06F3/06 ,  H01L23/538 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/22 ,  G06F11/10 ,  H01L25/065 ,  H01L23/50 ,  G11C5/02 ,  G11C11/00 ,  H01L23/14 ,  G11C11/4097

Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

公开(公告)号：US10579578B2

公开(公告)日：2020-03-03

申请号：US15981703

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F13/00 ,  G06F13/42 ,  G06F15/167

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

公开(公告)号：US09129662B2

公开(公告)日：2015-09-08

申请号：US14223079

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1087 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22

Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.

Abstract translation: 本发明的实施例描述了将数据驱动到总线上。 这些实施例包括具有耦合到总线的数据捕获电路的数据驱动器电路。 数据采集​​电路相对于写入选通信号接收数据，并响应写入选通信号的第一个边缘并且响应于写入选通信号的第二个边缘的至少一个第二数位捕获数据的第一个数字。 数据驱动器电路包括反馈捕获电路，其以与数据捕获电路基本相同的方式捕获每个数字，并且产生指示何时锁存每个数字的锁存控制信号。 锁存控制信号被提供给写入控制电路，该写入控制电路确定哪个数字相对于定时首先被锁存，并且产生一个选择控制信号，以便按照接收数字的顺序将捕获的数字驱动到总线上。

公开(公告)号：US12243610B2

公开(公告)日：2025-03-04

申请号：US17821676

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/56

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

公开(公告)号：US20250045389A1

公开(公告)日：2025-02-06

申请号：US18763983

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Lance P. Johnson ,  Nathan A. Eckel ,  James Brian Johnson

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.

公开(公告)号：US20250045388A1

公开(公告)日：2025-02-06

申请号：US18763963

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Chun-Yi Liu ,  Lance P. Johnson ,  James Brian Johnson ,  Yang Lu

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

公开(公告)号：US20240194287A1

公开(公告)日：2024-06-13

申请号：US18525403

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C29/025

Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.

公开(公告)号：US11893245B2

公开(公告)日：2024-02-06

申请号：US17863994

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0676 ,  G06F3/0679

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.