公开(公告)号：US20210271614A1

公开(公告)日：2021-09-02

申请号：US16804895

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F3/06 ,  G06F1/10 ,  G06F1/324

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US11003375B2

公开(公告)日：2021-05-11

申请号：US16249808

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/00 ,  G06F11/00 ,  G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.

公开(公告)号：US10949293B2

公开(公告)日：2021-03-16

申请号：US16516897

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

公开(公告)号：US20200257588A1

公开(公告)日：2020-08-13

申请号：US16863966

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

公开(公告)号：US11907560B2

公开(公告)日：2024-02-20

申请号：US18049870

申请日：2022-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0644 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1076

Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.

公开(公告)号：US11726866B2

公开(公告)日：2023-08-15

申请号：US17885158

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/44 ,  G06F11/07 ,  G06F11/14 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G06F11/30 ,  G06F11/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F11/102 ,  G06F11/0793 ,  G06F11/1012 ,  G06F11/1044 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

公开(公告)号：US11663142B2

公开(公告)日：2023-05-30

申请号：US17468160

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/12 ,  G06F12/0804 ,  H03M13/27 ,  H03M13/00 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0804 ,  G06F12/0891 ,  H03M13/2782 ,  H03M13/6563 ,  H03M13/6566

Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

公开(公告)号：US11507516B2

公开(公告)日：2022-11-22

申请号：US16997811

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0895 ,  G06F12/0862

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

公开(公告)号：US11436144B2

公开(公告)日：2022-09-06

申请号：US16846266

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/0864 ,  G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US11422884B2

公开(公告)日：2022-08-23

申请号：US17211280

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C29/44 ,  G06F11/07 ,  G06F11/14 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G06F11/30 ,  G06F11/10 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.