公开(公告)号：US09705318B2

公开(公告)日：2017-07-11

申请号：US14246309

申请日：2014-04-07

Applicant: Micron Technology, Inc.

Inventor： Michael Chaine ,  Xiaofeng Fan

IPC: H02H9/04 ,  H01L27/02 ,  H01L29/74

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L29/7436

Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

公开(公告)号：US09490631B2

公开(公告)日：2016-11-08

申请号：US14275211

申请日：2014-05-12

Applicant: Micron Technology, Inc.

Inventor： Xiaofeng Fan ,  Michael Chaine ,  John David Porter

IPC: H02H3/22 ,  H02H9/04 ,  H01L27/02 ,  H05K1/02

CPC classification number: H02H9/044 ,  H01L27/0248 ,  H01L27/0251 ,  H02H9/046 ,  H05K1/0259

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract translation: 公开了用于保护电路免受过电压条件的设备和方法。 一个示例性设备包括耦合到要保护的电路的保护电路。 要保护的电路耦合到焊盘节点。 保护电路被配置为将电流从焊盘节点传导到参考电压节点，以保护电路免受超限电气状况的影响。 保护电路具有耦合到焊盘节点的触发电路，并被配置为响应于提供给具有超过触发电压的电压的焊盘节点的电压，触发分流电路以将电流从焊盘节点传导到参考电压节点。 在一些实施例中，触发电路与被保护的电路相匹配。

公开(公告)号：US09281682B2

公开(公告)日：2016-03-08

申请号：US13795425

申请日：2013-03-12

Applicant: Micron Technology, Inc.

Inventor： James Davis ,  Michael Chaine

IPC: H01L27/12 ,  H02H9/04 ,  H01L27/02

CPC classification number: H02H9/041 ,  H01L27/0262 ,  H02H9/046

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

Abstract translation: 公开了用于保护电路免受静电放电事件的电路，集成电路，装置和方法。 示例性装置包括耦合到节点并被配置为限制电压和放电与节点处的过电压事件相关联的电流的晶闸管。 过电压事件包括具有超过晶闸管的触发电压的幅度的负电压。 该示例设备还包括耦合到晶闸管并被配置为调整触发电压的幅度的晶体管。

公开(公告)号：US11901727B2

公开(公告)日：2024-02-13

申请号：US17525707

申请日：2021-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James Davis ,  Michael Chaine

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/041 ,  H01L27/0262 ,  H02H9/046

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

公开(公告)号：US11183837B2

公开(公告)日：2021-11-23

申请号：US16223352

申请日：2018-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James Davis ,  Michael Chaine

IPC: H02H9/04 ,  H01L27/02

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

公开(公告)号：US20140319697A1

公开(公告)日：2014-10-30

申请号：US14324958

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/62 ,  H01L21/82

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

Abstract translation: 本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。 在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电 互连。 第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。 在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

公开(公告)号：US08772086B2

公开(公告)日：2014-07-08

申请号：US13850803

申请日：2013-03-26

Applicant: Russell D. Slifer ,  Micron Technology, Inc.

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

Abstract translation: 本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。 在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电 互连。 第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。 在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

公开(公告)号：US20130214421A1

公开(公告)日：2013-08-22

申请号：US13850803

申请日：2013-03-26

Applicant: Russell D. Slifer ,  Russell D. Slifer ,  MICRON TECHNOLOGY, INC.

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.