公开(公告)号：US10885959B1

公开(公告)日：2021-01-05

申请号：US16591461

申请日：2019-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ryosuke Yatsushiro ,  Seiji Narui

IPC: G11C5/06 ,  G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  H01L25/065 ,  H01L25/18

Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.

公开(公告)号：US10614024B2

公开(公告)日：2020-04-07

申请号：US15987895

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G11C11/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US20190304512A1

公开(公告)日：2019-10-03

申请号：US15938819

申请日：2018-03-28

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui

IPC: G11C5/02 ,  H01L25/065 ,  H01L27/105 ,  G11C5/04

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

公开(公告)号：US20210104269A1

公开(公告)日：2021-04-08

申请号：US17122801

申请日：2020-12-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ryosuke Yatsushiro ,  Seiji Narui

IPC: G11C7/22 ,  G11C7/10 ,  H01L25/065 ,  H01L25/18 ,  G11C8/18

Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.

公开(公告)号：US10553263B2

公开(公告)日：2020-02-04

申请号：US16225303

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/22 ,  G11C16/32 ,  G11C19/28 ,  G11C7/10

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US20190361835A1

公开(公告)日：2019-11-28

申请号：US15987895

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G06F13/42 ,  H01L27/108 ,  G11C11/402 ,  G11C11/4093

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US10185652B2

公开(公告)日：2019-01-22

申请号：US15606956

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G11C7/06 ,  G06F12/02 ,  H01L23/522

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US20180357156A1

公开(公告)日：2018-12-13

申请号：US16107963

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G06F12/02 ,  H01L23/522

CPC classification number: G06F12/02 ,  G06F2212/1016 ,  G06F2212/1028 ,  H01L23/5226

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US11869580B2

公开(公告)日：2024-01-09

申请号：US17565951

申请日：2021-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomohiko Yamagishi ,  Seiji Narui ,  Kiyoshi Nakai ,  Takamasa Suzuki

IPC: G11C11/4096 ,  G11C29/42 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C29/42

Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.

公开(公告)号：US11763855B2

公开(公告)日：2023-09-19

申请号：US17316140

申请日：2021-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiji Narui

IPC: G11C5/02 ,  H01L25/065 ,  G11C5/04 ,  H10B99/00

CPC classification number: G11C5/025 ,  G11C5/04 ,  H01L25/0657 ,  H10B99/00 ,  H01L2225/06541 ,  H01L2225/06555

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.