公开(公告)号：US20230117364A1

公开(公告)日：2023-04-20

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

公开(公告)号：US20220351782A1

公开(公告)日：2022-11-03

申请号：US17868703

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Foroozan S. Koushan ,  Shinji Sato

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32

Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.

公开(公告)号：US11574690B2

公开(公告)日：2023-02-07

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

公开(公告)号：US09916901B1

公开(公告)日：2018-03-13

申请号：US15416870

申请日：2017-01-26

Applicant: Micron Technology, Inc.

Inventor： Masanobu Saito ,  Shuji Tanaka ,  Shinji Sato

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.