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公开(公告)号：US20170154663A1
公开(公告)日：2017-06-01
申请号：US15431383
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
IPC: G11C11/406 , G11C11/408 , G11C11/4076
CPC classification number: G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093
Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
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公开(公告)号：US09570142B2
公开(公告)日：2017-02-14
申请号：US14714962
申请日：2015-05-18
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
IPC: G11C7/00 , G11C11/406 , G11C11/4076
CPC classification number: G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093
Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
Abstract translation: 一些实施例包括一种装置，其包括具有产生原始时钟信号的振荡器的接口芯片，具有第一存储器单元的第一存储器芯片和具有第二存储器单元的第二存储器芯片。 可以响应于基于原始时钟信号的第一时钟信号来刷新第一存储器单元。 响应于基于原始时钟信号的第二时钟信号可以刷新第二存储器单元。
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公开(公告)号：US20160343423A1
公开(公告)日：2016-11-24
申请号：US14714962
申请日：2015-05-18
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
IPC: G11C11/406 , G11C11/4076
CPC classification number: G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093
Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
Abstract translation: 一些实施例包括一种装置，其包括具有产生原始时钟信号的振荡器的接口芯片，具有第一存储器单元的第一存储器芯片和具有第二存储器单元的第二存储器芯片。 可以响应于基于原始时钟信号的第一时钟信号来刷新第一存储器单元。 响应于基于原始时钟信号的第二时钟信号可以刷新第二存储器单元。
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公开(公告)号：US10553263B2
公开(公告)日：2020-02-04
申请号：US16225303
申请日：2018-12-19
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号：US20180293128A1
公开(公告)日：2018-10-11
申请号：US15983073
申请日：2018-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chiaki Dono , Seiichi Maruno , Taihei Shido , Toshio Ninomiya , Chikara Kondo
IPC: G06F11/10
CPC classification number: G06F11/1004 , G06F11/1016
Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
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Patent Agency Ranking
公开(公告)号：US10008254B2
公开(公告)日：2018-06-26
申请号：US15431383
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
IPC: G11C5/06 , G11C11/406 , G11C11/4076 , G11C11/408
CPC classification number: G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093
Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
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公开(公告)号：US09983925B2
公开(公告)日：2018-05-29
申请号：US14678375
申请日：2015-04-03
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono , Seiichi Maruno , Taihei Shido , Toshio Ninomiya , Chikara Kondo
CPC classification number: G06F11/1004 , G06F11/1016
Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.
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公开(公告)号：US20180025789A1
公开(公告)日：2018-01-25
申请号：US15217719
申请日：2016-07-22
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono , Taihei Shido , Yuki Ebihara
Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
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公开(公告)号：US10943625B2
公开(公告)日：2021-03-09
申请号：US16721515
申请日：2019-12-19
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号：US10468114B2
公开(公告)日：2019-11-05
申请号：US16013290
申请日：2018-06-20
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono , Taihei Shido , Yuki Ebihara
Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
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