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公开(公告)号：US20230359563A1
公开(公告)日：2023-11-09
申请号：US17630453
申请日：2021-03-16
Applicant: Micron Technology, Inc.
IPC: G06F12/0873
CPC classification number: G06F12/0873
Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
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公开(公告)号：US20220357877A1
公开(公告)日：2022-11-10
申请号：US17869262
申请日：2022-07-20
Applicant: Micron Technology, Inc.
Inventor： Huachen Li , Xu Zhang , Zhong Xian Li , Xinghui Duan , Xing Wang , Tian Liang
IPC: G06F3/06 , G06F12/02 , G06F12/0882
Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).
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公开(公告)号：US20240411483A1
公开(公告)日：2024-12-12
申请号：US18749469
申请日：2024-06-20
Applicant: Micron Technology, Inc.
Inventor： Huachen Li , Xu Zhang , Xing Wang , Guan Zhong Wang , Tian Liang , Junjun Wang
IPC: G06F3/06
Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.
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公开(公告)号：US20240295971A1
公开(公告)日：2024-09-05
申请号：US18604118
申请日：2024-03-13
Applicant: Micron Technology, Inc.
Inventor： Xing Wang , Liu Yang , Xiaolai Zhu , Bin Zhao
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/064 , G06F3/0679
Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.
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公开(公告)号：US12019543B2
公开(公告)日：2024-06-25
申请号：US17890511
申请日：2022-08-18
Applicant: Micron Technology, Inc.
IPC: G06F12/08 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A system includes a memory device having an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache, the processing device to perform operations including: detecting demand for the cache during a memory operation requiring access to the single-level cell memory; and causing metadata associated with the memory operation to be stored in one or more page buffers of the plurality of page buffers, the one or more page buffers operating as an extension of the cache available to the processing device.
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Patent Agency Ranking
公开(公告)号：US20240061778A1
公开(公告)日：2024-02-22
申请号：US17890511
申请日：2022-08-18
Applicant: Micron Technology, Inc.
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A system includes a memory device having an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache, the processing device to perform operations including: detecting demand for the cache during a memory operation requiring access to the single-level cell memory; and causing metadata associated with the memory operation to be stored in one or more page buffers of the plurality of page buffers, the one or more page buffers operating as an extension of the cache available to the processing device.
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公开(公告)号：US20230359365A1
公开(公告)日：2023-11-09
申请号：US17630113
申请日：2021-03-16
Applicant: Micron Technology, Inc.
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0634 , G06F3/0679 , G06F3/0659
Abstract: Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.
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公开(公告)号：US20240311299A1
公开(公告)日：2024-09-19
申请号：US18672310
申请日：2024-05-23
Applicant: Micron Technology, Inc.
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.
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公开(公告)号：US11954336B2
公开(公告)日：2024-04-09
申请号：US17637428
申请日：2021-03-18
Applicant: Micron Technology, Inc.
Inventor： Xing Wang , Liu Yang , Xiaolai Zhu , Bin Zhao
CPC classification number: G06F3/0622 , G06F3/064 , G06F3/0679
Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.
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公开(公告)号：US20240078031A1
公开(公告)日：2024-03-07
申请号：US17929966
申请日：2022-09-06
Applicant: Micron Technology, Inc.
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0652 , G06F3/0655 , G06F3/0679
Abstract: Methods, systems, and devices for dividing blocks for special functions are described. Some memory systems may be configured to assign a block of the memory system as a special function block configured with a first portion for storing information associated with a first function of the memory system and a second portion for storing information associated with a second function of the memory system; write a first set of information to the first portion of the block based at least in part on assigning the block as the special function block, the first set of information associated with the first function of the memory system; and write a second set of information to the second portion of the block based at least in part on assigning the block as the special function block, the second set of information associated with the second function of the memory system.
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