公开(公告)号：US11443788B1

公开(公告)日：2022-09-13

申请号：US17204063

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He ,  Hyunui Lee

IPC: G11C5/14 ,  G11C8/08 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

公开(公告)号：US20220223191A1

公开(公告)日：2022-07-14

申请号：US17144461

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He

IPC: G11C11/4074

Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

公开(公告)号：US11139019B1

公开(公告)日：2021-10-05

申请号：US17177025

申请日：2021-02-16

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: H03K5/01 ,  G11C11/4076 ,  H03K19/20 ,  H03K3/037 ,  H03L7/081 ,  G11C19/28 ,  H03K5/00

Abstract: Apparatuses and methods for correcting a code used for delay adjustment are disclosed. An example method includes providing a bit of a thermometer code responsive, at least, to a shift direction signal; and adjusting an amount of a delay responsive to the thermometer code. Providing the bit comprises correcting the bit using one or more adjacent bits on one side of the bit in the thermometer code and one or more adjacent bits on another side of the bit in the thermometer code.

公开(公告)号：US20210065782A1

公开(公告)日：2021-03-04

申请号：US16559344

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US10931289B2

公开(公告)日：2021-02-23

申请号：US16536079

申请日：2019-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/183 ,  H03L7/193 ,  H03K5/13 ,  H03L7/08 ,  H03K21/10 ,  H03L7/099

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

公开(公告)号：US20190296752A1

公开(公告)日：2019-09-26

申请号：US16440818

申请日：2019-06-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/099 ,  H03L7/089 ,  H03L7/10 ,  H03L7/081

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US20190214072A1

公开(公告)日：2019-07-11

申请号：US15868232

申请日：2018-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh ,  Tyler J. Gomm

IPC: G11C11/4076 ,  H03K3/017 ,  G11C29/02 ,  H03K23/00 ,  H03M7/16

CPC classification number: G11C11/4076 ,  G11C29/023 ,  H03K3/017 ,  H03K5/1565 ,  H03K19/21 ,  H03K23/005 ,  H03M7/16

Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

公开(公告)号：US10110240B1

公开(公告)日：2018-10-23

申请号：US15786362

申请日：2017-10-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/06 ,  H03L7/193 ,  H03K5/13 ,  H03L7/08 ,  H03K21/10

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

公开(公告)号：US20240250675A1

公开(公告)日：2024-07-25

申请号：US18624648

申请日：2024-04-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  G11C11/4076

CPC classification number: H03K5/1565 ,  G11C11/4076

Abstract: An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.

公开(公告)号：US11973506B2

公开(公告)日：2024-04-30

申请号：US17845764

申请日：2022-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  G11C11/4076

CPC classification number: H03K5/1565 ,  G11C11/4076

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.