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公开(公告)号：US20220188247A1
公开(公告)日：2022-06-16
申请号：US17117933
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Chulbum Kim , Mark A. Helm , Yoav Weinberg
Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.
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公开(公告)号：US20220027284A1
公开(公告)日：2022-01-27
申请号：US17494740
申请日：2021-10-05
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Carminantonio Manganelli , Paolo Papa , Yoav Weinberg , Giuseppe Ferrari , Massimo Iaculo , Lalla Fatima Drissi
IPC: G06F12/1009
Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.
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公开(公告)号：US12301254B2
公开(公告)日：2025-05-13
申请号：US17829913
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Mustafa N. Kaynak , Yoav Weinberg , Zhengang Chen , Sivagnanam Parthasarathy
IPC: H03M13/11
Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.
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公开(公告)号：US12170124B2
公开(公告)日：2024-12-17
申请号：US17692262
申请日：2022-03-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.
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公开(公告)号：US12111781B2
公开(公告)日：2024-10-08
申请号：US18119576
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
CPC classification number: G06F13/30 , G06F13/1668
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
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Patent Agency Ranking
公开(公告)号：US20240231685A9
公开(公告)日：2024-07-11
申请号：US18048292
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0631 , G06F3/0673
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
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公开(公告)号：US11914473B1
公开(公告)日：2024-02-27
申请号：US18048289
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Tal Sharifie , Chandrakanth Rapalli , Yoav Weinberg
CPC classification number: G06F11/1068 , G06F11/0793 , G06F11/1004
Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
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18.发明公开公开(公告)号：US20230396271A1
公开(公告)日：2023-12-07
申请号：US17829913
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Mustafa N. Kaynak , Yoav Weinberg , Zhengang Chen , Sivagnanam Parthasarathy
IPC: H03M13/11
CPC classification number: H03M13/1117 , H03M13/1108 , H03M13/1151
Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.
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19.发明公开公开(公告)号：US20230396269A1
公开(公告)日：2023-12-07
申请号：US17829924
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Yoav Weinberg
CPC classification number: H03M13/1108 , H03M13/1148 , H03M13/1128 , H03M13/6511
Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
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公开(公告)号：US20230289306A1
公开(公告)日：2023-09-14
申请号：US18119576
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
CPC classification number: G06F13/30 , G06F13/1668
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
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