公开(公告)号：US20210167798A1

公开(公告)日：2021-06-03

申请号：US17170259

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: H03M13/11 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

公开(公告)号：US20200278908A1

公开(公告)日：2020-09-03

申请号：US16803856

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US20190179700A1

公开(公告)日：2019-06-13

申请号：US15839617

申请日：2017-12-12

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/406 ,  G11C11/22

Abstract: Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.

公开(公告)号：US09378791B2

公开(公告)日：2016-06-28

申请号：US14800512

申请日：2015-07-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/00

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

公开(公告)号：US11314591B2

公开(公告)日：2022-04-26

申请号：US17017254

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00 ,  G11C29/04 ,  G06F13/42

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：US20210311829A1

公开(公告)日：2021-10-07

申请号：US17348211

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US11061771B2

公开(公告)日：2021-07-13

申请号：US16803856

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US10860469B2

公开(公告)日：2020-12-08

申请号：US16448297

申请日：2019-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G06F12/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C7/22 ,  G06F1/06 ,  G11C11/408 ,  G06F1/12

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US20200169269A1

公开(公告)日：2020-05-28

申请号：US16199773

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

公开(公告)号：US10534394B2

公开(公告)日：2020-01-14

申请号：US16138517

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G06F1/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C7/22 ,  G11C11/408 ,  G06F1/12

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.