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公开(公告)号：US20220261345A1
公开(公告)日：2022-08-18
申请号：US17736824
申请日：2022-05-04
Applicant: Micron Technology Inc.
Inventor： Mikai Chen , Zhengang Chen , Charles See Yeung Kwong
Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.
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公开(公告)号：US20210042224A1
公开(公告)日：2021-02-11
申请号：US16531305
申请日：2019-08-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mikai Chen , Zhengang Chen , Charles See Yeung Kwong
Abstract: Data can be received to be stored at a memory component. A first location of a first layer of the memory component to store a first portion of the data can be determined. A second location of a second layer of the memory component to store a second portion of the data can be determined, where the second layer is different from the first layer. The first portion of the data can be stored at the first layer of the memory component and the second portion of the data can be stored at the second layer of the memory component.
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13.发明公开公开(公告)号：US20240347116A1
公开(公告)日：2024-10-17
申请号：US18755046
申请日：2024-06-26
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC classification number: G11C16/3431 , G11C16/0483
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.
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公开(公告)号：US20240329852A1
公开(公告)日：2024-10-03
申请号：US18739982
申请日：2024-06-11
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
Abstract: A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US12050777B2
公开(公告)日：2024-07-30
申请号：US17880213
申请日：2022-08-03
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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Patent Agency Ranking
公开(公告)号：US11914510B2
公开(公告)日：2024-02-27
申请号：US17736824
申请日：2022-05-04
Applicant: Micron Technology Inc.
Inventor： Mikai Chen , Zhengang Chen , Charles See Yeung Kwong
CPC classification number: G06F12/0607 , G06F12/0207 , G06F2212/1032
Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.
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17.发明授权公开(公告)号：US11495279B1
公开(公告)日：2022-11-08
申请号：US17402984
申请日：2021-08-16
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon
IPC: G11C11/406 , G11C29/42 , G11C11/4096
Abstract: A write operation performed on a first memory unit of a memory device is detected, wherein the first memory unit comprises one or more memory cells. Responsive to detecting the write operation, a value of a counter associated with the first memory unit is incremented. It is determined whether the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range. Responsive to determining that the value of the counter satisfies the threshold criterion, a refresh operation is performed on a second memory unit.
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公开(公告)号：US11341046B2
公开(公告)日：2022-05-24
申请号：US16531305
申请日：2019-08-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mikai Chen , Zhengang Chen , Charles See Yeung Kwong
Abstract: Data can be received to be stored at a memory component. A first location of a first layer of the memory component to store a first portion of the data can be determined. A second location of a second layer of the memory component to store a second portion of the data can be determined, where the second layer is different from the first layer. The first portion of the data can be stored at the first layer of the memory component and the second portion of the data can be stored at the second layer of the memory component.
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公开(公告)号：US11056166B2
公开(公告)日：2021-07-06
申请号：US16514840
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Seungjune Jeon , Zhengang Chen , Zhenlei Shen , Charles See Yeung Kwong
IPC: G11C7/00 , G11C11/406 , G11C11/16
Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.
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公开(公告)号：US20240320077A1
公开(公告)日：2024-09-26
申请号：US18672635
申请日：2024-05-23
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon , Wei Wang , Zhenming Zhou
CPC classification number: G06F11/076 , G06F11/008 , G06F11/073 , G06F2201/81 , G06F2212/7211
Abstract: A first blocks of a set of blocks of a memory device is identified. A die on which the first block resides is identified among a plurality of dies of the memory device. A threshold value associated with the die is selected from a range associated with a projected reliability metric of the die. Responsive to determining that an endurance metric value associated with the die matches the threshold value, a program operation is performed with respect to a second block of the set of blocks.
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