公开(公告)号：US10783951B2

公开(公告)日：2020-09-22

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US10783949B2

公开(公告)日：2020-09-22

申请号：US16417004

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C7/06 ,  G11C7/00 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/16 ,  G11C11/56

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US10658024B2

公开(公告)日：2020-05-19

申请号：US16523653

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US10580464B2

公开(公告)日：2020-03-03

申请号：US16429510

申请日：2019-06-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06 ,  H01L27/108 ,  H01L27/092 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/822 ,  H01L21/8238

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US20200051613A1

公开(公告)日：2020-02-13

申请号：US16404525

申请日：2019-05-06

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4097

Abstract: Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.

公开(公告)号：US20190333564A1

公开(公告)日：2019-10-31

申请号：US16417004

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US10431291B1

公开(公告)日：2019-10-01

申请号：US16058600

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US10418083B2

公开(公告)日：2019-09-17

申请号：US16058202

申请日：2018-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US10276230B2

公开(公告)日：2019-04-30

申请号：US15664140

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4097 ,  G11C11/4094 ,  G11C7/02 ,  G11C11/408 ,  H01L27/108 ,  G11C11/4091

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20190096894A1

公开(公告)日：2019-03-28

申请号：US16204409

申请日：2018-11-29

Applicant: Micron Technology Inc.

Inventor： Debra M. Bell ,  Scott J. Derner

IPC: H01L27/11 ,  H01L21/762 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1112 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76202 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1108

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.