公开(公告)号：US07376016B2

公开(公告)日：2008-05-20

申请号：US11488621

申请日：2006-07-19

申请人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

发明人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3459

摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US07339833B2

公开(公告)日：2008-03-04

申请号：US11481782

申请日：2006-07-07

申请人： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

发明人： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

摘要： Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.

摘要翻译： 使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。 电容元件的电容值根据写入数据的值而变化。 实现了以高精度写入多值数据的非易失性半导体存储器件。

公开(公告)号：US07102953B2

公开(公告)日：2006-09-05

申请号：US11030185

申请日：2005-01-07

申请人： Takashi Kono ,  Hironori Iga

发明人： Takashi Kono ,  Hironori Iga

IPC分类号： G11C5/14

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

摘要： A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

摘要翻译： 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，从而可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

公开(公告)号：US06894940B2

公开(公告)日：2005-05-17

申请号：US10625588

申请日：2003-07-24

申请人： Takashi Kono ,  Takeshi Hamamoto

发明人： Takashi Kono ,  Takeshi Hamamoto

IPC分类号： H01L21/8242 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4097 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

摘要： A sense amplifier driving line is connected to the source of an N-channel MOS transistor. Accordingly, even if a control signal attains H level, a sub-amplifier will not operate. This is because the sense amplifier driving line and an LIO line pair both attain a precharge potential, and a gate-source voltage of an N-channel MOS transistor attains 0V. Thus, it is not necessary to add a circuit configuration for supplying a signal notifying of activation of a row block, and a semiconductor memory device with a smaller area is obtained.

摘要翻译： 读出放大器驱动线连接到N沟道MOS晶体管的源极。 因此，即使控制信号达到H电平，子放大器也不会运行。 这是因为读出放大器驱动线和LIO线对都达到预充电电位，并且N沟道MOS晶体管的栅极 - 源极电压达到0V。 因此，不需要添加用于提供通知行块的激活的信号的电路配置，并且获得具有较小面积的半导体存储器件。

公开(公告)号：US06753720B2

公开(公告)日：2004-06-22

申请号：US10302849

申请日：2002-11-25

申请人： Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

发明人： Takashi Kono ,  Katsuyoshi Mitsui ,  Kiyohiro Furutani

IPC分类号： G05F110

CPC分类号： G05F1/465 ,  G11C5/143 ,  G11C5/145

摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

摘要翻译： 为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态 初始控制电路。

公开(公告)号：US06741521B2

公开(公告)日：2004-05-25

申请号：US10253928

申请日：2002-09-25

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/107

摘要： Data of 2-bits prefetched from a memory array and transmitted to an amplifying circuit via a data bus is ordered in accordance with the least significant bit of a column address which is a start address supplied from the outside. The first data is output to read data buses and is directly transmitted to an output data latch. The second data is held once by a second data latch and, after that, transmitted to the output data latch. Since the first data is transmitted from the amplifying circuit directly to the output data latch, the time from a read command is received until data is started to be output can be shortened.

摘要翻译： 根据从外部提供的起始地址的列地址的最低有效位来排序从存储器阵列预取并经由数据总线发送到放大电路的2位的数据。 第一数据被输出以读取数据总线，并直接发送到输出数据锁存器。 第二数据由第二数据锁存器保持一次，之后被发送到输出数据锁存器。 由于第一数据从放大电路直接发送到输出数据锁存器，所以从读取命令开始的时间直到数据开始输出才能被缩短。

公开(公告)号：US06714471B2

公开(公告)日：2004-03-30

申请号：US10270653

申请日：2002-10-16

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  G11C2207/107

摘要： A preamplifier includes an amplifier circuit amplifying a signal level of read data, a latency shifter outputting the read data onto a data line pair in response to an internal signal determining a timing of outputting the read data onto the data bus pair, and a driver outputting the read data onto the data bus pair. The amplifier circuit receives the internal signal and outputs the read data onto the data line pair while bypassing the latency shifter when the internal signal is already at high level at the timing when the signal level of the read data is amplified. As a result, a semiconductor memory device can speed up propagation of the read data from the preamplifier onto the data bus pair in a high frequency operation.

摘要翻译： 前置放大器包括：放大电路，放大读取数据的信号电平;延迟移位器响应于确定将读出的数据输出到数据总线对上的定时的内部信号，将读出的数据输出到数据线对;以及驱动器输出 将数据读取到数据总线上。 当读取数据的信号电平被放大的定时，当内部信号已经处于高电平时，放大器电路接收内部信号并将读取的数据输出到数据线对上，同时绕过等待时间移位器。 结果，半导体存储器件可以在高频操作中加速读取数据从前置放大器传播到数据总线对上。

公开(公告)号：US06707758B2

公开(公告)日：2004-03-16

申请号：US10234240

申请日：2002-09-05

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/107

摘要： A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.

摘要翻译： DLL电路产生从外部时钟延迟适当量的第一和第二内部时钟，并且产生第三和第四内部时钟，其能够在基于内部信号的第一和第二内部时钟的CAS等待时间之后驱动数据输出电路 。 中继器恢复第三和第四内部时钟的信号电平，并将第三和第四内部时钟作为DLL时钟输出。 数据输出电路使用从中继器输出的DLL时钟，读取数据，并将读出的数据以与DLL时钟同步的半周期的形式输出到外部。 以这种方式，可以通过在数据输出电路的前一级生成DLL时钟来减少半导体存储器件的电路面积。

公开(公告)号：US06392944B1

公开(公告)日：2002-05-21

申请号：US09985283

申请日：2001-11-02

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C708

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074

摘要： A semiconductor memory device includes two power feed lines. An overdriving scheme is applied to one of the power feed lines in the sensing amplifying operation, and no overdriving scheme is applied to the other power feed line in the sensing operation. According to the overdriving scheme, the power feed line is overdriven to a potential level higher than a potential corresponding high level data stored in a memory cell. Thus, the overdriving of the power feed line is applied as an auxiliary function to prevent application of an excess potential to a memory cell capacitor. Such a semiconductor memory device can be achieved that improves both the speed of sensing amplifying operation and the reliability of memory cell capacitors, while conforming to low voltage operation requirement.

摘要翻译： 半导体存储器件包括两个馈电线。 在感测放大操作中，对一个馈电线路施加过驱动方案，并且在感测操作中不将过驱动方案应用于另一馈电线路。 根据过驱动方案，馈电线被过驱动到高于存储在存储单元中的电位对应的高电平数据的电位电平。 因此，作为辅助功能施加供电线的过驱动，以防止对存储单元电容器施加过多的电位。 可以实现这样的半导体存储器件，其在符合低电压操作要求的同时，提高了感测放大操作的速度和存储单元电容器的可靠性。

公开(公告)号：US06297624B1

公开(公告)日：2001-10-02

申请号：US09258159

申请日：1999-02-26

申请人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

发明人： Katsuyoshi Mitsui ,  Kiyohiro Furutani ,  Takashi Kono

IPC分类号： G05F316

CPC分类号： G05F1/465

摘要： An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.

摘要翻译： 内部电源电路从外部电源电压产生内部电源电压。 电压电平控制电路控制由内部电源电路产生的内部电源电压的电压电平和温度特性。 内部电源电路在低温区域产生具有负温度或零温度特性的内部电源电压，在高温区域产生正温度特性。 电压电平控制电路包括优化用于驱动读出放大器电路的感测电源线稳定电容的电容值的结构，确定内部电源电路的外部电源电压的最低可操作区域的电平转换电路，或 一个在上电时强制运行内部降压转换器的结构。 以小的占用面积和低的电流消耗稳定地产生期望的内部电源电压。