公开(公告)号：US5796135A

公开(公告)日：1998-08-18

申请号：US960142

申请日：1997-10-29

申请人： Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang ,  Chung-Hui Su

发明人： Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang ,  Chung-Hui Su

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/11 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10844 ,  H01L27/1052 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/105 ,  Y10S257/903

摘要： A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.

摘要翻译： 已经开发了用于集成堆叠电容器，DRAM器件和薄膜晶体管SRAM器件的制造工艺。 该制造工艺具有组合用于产生传输门晶体管结构的关键操作的特征，以及用于DRAM和SRAM器件的存取晶体管结构。 此外，用于为SRAM器件创建用于DRAM器件的电容器结构和薄膜晶体管结构的工艺步骤也被共享。 本发明的另一个关键特征是用于SRAM器件的掩埋接触结构。

公开(公告)号：US5677557A

公开(公告)日：1997-10-14

申请号：US742129

申请日：1996-10-31

申请人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/76 ,  H01L31/113 ,  H01L29/54 ,  H01L31/262

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

摘要翻译： 实现了一种用于多晶硅层互连的埋地金属插塞结构的制造方法以及用于同时制造诸如DRAM和SRAM的半导体集成电路上的金属插头的方法。 该方法涉及在图案化的多晶硅层中的开口上形成绝缘层中的接触开口。 多晶硅层中的开口对准衬底上的源/漏接触区域，并提供用于形成自对准接触开口的装置。 接触开口中埋入的金属塞形成多晶硅层与源极/漏极之间的互连。 并且，通过合并工艺步骤，同时形成用于触点的金属插头互连件到半导体器件和第一级金属。 该过程适用于在DRAM和SRAM电路上形成位线触点，同时在芯片上形成周边触点。

公开(公告)号：US5668380A

公开(公告)日：1997-09-16

申请号：US612398

申请日：1996-03-07

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L21/285 ,  H01L23/485 ,  H01L27/11 ,  H01L29/45 ,  H01L29/76 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L27/1108 ,  H01L21/28512 ,  H01L23/485 ,  H01L29/458 ,  H01L2924/0002 ,  Y10S257/903

摘要： Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The structure provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The structure further allows process steps to be used that provide larger latitude in etching the contact opening and thereby provides a structure that is very manufacturable.

摘要翻译： 实现了具有低欧姆电阻的薄区域金属接触到薄的多晶硅层接触结构。 该结构涉及在由厚的多晶硅层构成的缓冲层上形成绝缘层中的接触开口。 开口中的侧壁的一部分包括形成半导体器件的一部分并且还形成与金属接触件的电连接的图案化的多晶硅层。 该结构提供具有非常低的电阻和减小面积的金属接触以增加器件封装密度。 金属接触结构也消除了形成通常与P + / N +堆叠接触相关联的P + / N +非欧姆结的问题。 该结构进一步允许使用在蚀刻接触开口时提供较大纬度的工艺步骤，从而提供非常可制造的结构。

公开(公告)号：US5547892A

公开(公告)日：1996-08-20

申请号：US429725

申请日：1995-04-27

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L27/1108 ,  Y10S148/02

摘要： A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (I.sub.on) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate.

摘要翻译： 实现了一种用于制造用于低电阻欧姆堆叠触点的新型插头结构并同时与SRAM单元上的器件形成金属触点的方法。 该方法包括在堆叠的接触开口中形成导电插塞以在P +掺杂多晶硅层和N +掺杂多晶硅层之间形成欧姆连接，从而增加SRAM单元的导通电流（Ion）。 导电插塞也同时形成在金属接触开口中，到基片上别处的器件区域。

公开(公告)号：US5545584A

公开(公告)日：1996-08-13

申请号：US498677

申请日：1995-07-03

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/1108

摘要： A method was achieved for making a static random access memory SRAM by integrating or merging into the SRAM process a unified contact plug process that reduces the number of processing steps and forms low resistance ohmic contacts between N.sup.+ and P.sup.+ polysilicon layers. The plug process utilizes patterned features in the multi-layers of polysilicon and the high selective etching of silicon oxide to polysilicon to form all the contact concurrently, and thereby eliminate the need to etch contacts openings between each polysilicon layer. The unified contact plug method was demonstrate on the SRAM for making the a buried contacts for the node contacts on the SRAM, the bit line contacts and a V.sub.ss contact for the ground plane in the SRAM cell.

摘要翻译： 通过将静态随机存取存储器SRAM集成或并入到SRAM处理中，可以减少处理步骤数量并形成N +和P +多晶硅层之间的低电阻欧姆接触的统一的接触插塞处理方法。 插塞过程利用多层多晶硅中的图案化特征以及将氧化硅高选择性蚀刻到多晶硅以同时形成所有接触，从而消除了蚀刻每个多晶硅层之间的接触开口的需要。 在SRAM上展示了统一的接触插塞方法，用于为SRAM中的节点触点，位线触点和SRAM单元中接地平面的Vss触点提供埋地触点。

公开(公告)号：US5480814A

公开(公告)日：1996-01-02

申请号：US365049

申请日：1994-12-27

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chuan-Jung Wang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chuan-Jung Wang ,  Chung-Hui Su

IPC分类号： H01L21/60 ,  H01L21/265 ,  H01L21/44 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76897

摘要： A method for forming a metal contact in a self aligned contact region over a impurity region in a substrate which comprises forming a doped polysilicon layer over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer, preferably tungsten, are then formed over the polysilicon layer and the contact area. The resulting metal contact has superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.

摘要翻译： 一种用于在衬底中的杂质区域上的自对准接触区域中形成金属接触的方法，其包括在除了接触区域之外的器件表面上形成掺杂多晶硅层。 然后在多晶硅层和接触区域上形成薄的多晶硅阻挡层和金属层，优选为钨。 所得到的金属接触具有优异的台阶覆盖率，较低的电阻率，并保持了埋入杂质区域的浅结深度。

公开(公告)号：US5731232A

公开(公告)日：1998-03-24

申请号：US745639

申请日：1996-11-08

申请人： Shou-Gwo Wuu ,  Mong-Song Liang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/84 ,  Y10S257/903

摘要： A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.- doped third polySi layer is deposited, selectively doped P.sup.+ and patterned to form the TFT N.sup.- doped channel, the P.sup.+ doped source/drains, and the interconnection in the contact openings to the N-FET gate electrodes. The conductor at the interface between the P/N polySi forms essentially ohmic contacts, thereby eliminating the P/N junction and improving circuit performance.

摘要翻译： 实现了薄膜晶体管（TFT）栅电极由电导体制成的TFT负载静态随机存取存储器（SRAM）单元的方法。 同时，P和N掺杂多晶硅互连之间的导体部分消除了P / N结。 在避免额外的处理步骤的同时形成欧姆接触。 N沟道FET栅极由其上具有第一绝缘层的N +掺杂的第一多晶硅层形成。 第二多晶硅互连在其上形成有第二绝缘层。 第一接触开口在第一和第二绝缘层中蚀刻到N +掺杂FET栅电极，并且图案化导体（TiN，TiSi 2）形成P沟道TFT栅电极，同时在第一接触开口上并在其中形成部分。 形成TFT栅极氧化物，并且第二接触开口在第一接触开口上蚀刻到导体。 沉积N-掺杂的第三多晶硅层，选择性掺杂P +并图案化以形成TFT N掺杂沟道，P +掺杂源极/漏极以及在N-FET栅电极的接触开口中的互连。 在P / N多晶硅之间的界面处的导体形成基本的欧姆接触，从而消除P / N结并提高电路性能。

公开(公告)号：US5796150A

公开(公告)日：1998-08-18

申请号：US899673

申请日：1997-07-24

申请人： Shou-Gwo Wuu ,  Kan-Yuan Lee ,  Mong-Song Liang

发明人： Shou-Gwo Wuu ,  Kan-Yuan Lee ,  Mong-Song Liang

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L9/94

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A method for fabricating thin film transistors (TFTS) for SRAM devices is described having metal shields over the channel regions for improved electrical characteristics. The method involves forming N.sup.+ doped polysilicon TFT gate electrodes having a gate oxide thereon. An N.sup.- doped amorphous silicon is deposited and recrystallized. The recrystallized silicon is P.sup.+ doped to form the TFT source/drain areas and patterned to form the N.sup.- doped channel regions with P.sup.+ source/drain areas. After depositing an insulating layer, a metal layer is deposited and patterned to completely cover and shield the TFT channel regions from ion damage during the plasma hydrogenation which is subsequently performed. The patterned metal layer also serves as the bit lines for the SRAM device. The plasma hydrogenation reduces the surface states at the gate oxide channel interface, while the shielding effect of the metal layer from ion damaging radiation reduces the off current (I.sub.off), increases the I.sub.on /I.sub.off ratio of the TFTs, and improves the long-term reliability of the threshold voltage (V.sub.t) and swing (S) of the TFT over the unshielded TFT.

摘要翻译： 描述了一种用于制造用于SRAM器件的薄膜晶体管（TFTS）的方法，其在通道区域上具有用于改善电特性的金属屏蔽。 该方法包括在其上形成具有栅极氧化物的N +掺杂多晶硅TFT栅电极。 沉积N-掺杂的非晶硅并重结晶。 再结晶的硅是P +掺杂以形成TFT源极/漏极区域并被图案化以形成具有P +源极/漏极区域的N掺杂沟道区域。 在沉积绝缘层之后，沉积和图案化金属层以完全覆盖和屏蔽TFT沟道区域，以免在后续进行的等离子体氢化期间的离子损伤。 图案化金属层也用作SRAM器件的位线。 等离子体氢化降低了栅极氧化物沟道界面处的表面状态，而金属层从离子损伤辐射的屏蔽效应降低了截止电流（Ioff），增加了TFT的离子/离子比率，并改善了长期 在非屏蔽TFT上的TFT的阈值电压（Vt）和摆动（S）的可靠性。

公开(公告)号：US5686335A

公开(公告)日：1997-11-11

申请号：US684818

申请日：1996-07-22

申请人： Shou-Gwo Wuu ,  Kan-Yuan Lee ,  Mong-Song Liang

发明人： Shou-Gwo Wuu ,  Kan-Yuan Lee ,  Mong-Song Liang

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： A method for fabricating thin film transistors (TFTs) for SRAM devices is described having metal shields over the channel regions for improved electrical characteristics. The method involves forming N.sup.+ doped polysilicon TFT gate electrodes having a gate oxide thereon. An N.sup.- doped amorphous silicon is deposited and recrystallized. The recrystallized silicon is P.sup.+ doped to form the TFT source/drain areas and patterned to form the N.sup.- doped channel regions with P.sup.+ source/drain areas. After depositing an insulating layer, a metal layer is deposited and patterned to completely cover and shield the TFT channel regions from ion damage during the plasma hydrogenation which is subsequently performed. The patterned metal layer also serves as the bit lines for the SRAM device. The plasma hydrogenation reduces the surface states at the gate oxide channel interface, while the shielding effect of the metal layer from ion damaging radiation reduces the off current (I.sub.off), increases the I.sub.on /I.sub.off ratio of the TFTs, and improves the long-term reliability of the threshold voltage (V.sub.t) and swing (S) of the TFT over the unshielded TFT.

摘要翻译： 描述了一种用于制造用于SRAM器件的薄膜晶体管（TFT）的方法，其在通道区域上具有金属屏蔽以改善电气特性。 该方法包括在其上形成具有栅极氧化物的N +掺杂多晶硅TFT栅电极。 沉积N-掺杂的非晶硅并重结晶。 再结晶的硅是P +掺杂以形成TFT源极/漏极区域并被图案化以形成具有P +源极/漏极区域的N掺杂沟道区域。 在沉积绝缘层之后，沉积和图案化金属层以完全覆盖和屏蔽TFT沟道区域，以免在后续进行的等离子体氢化期间的离子损伤。 图案化金属层也用作SRAM器件的位线。 等离子体氢化降低了栅极氧化物沟道界面处的表面状态，而金属层从离子损伤辐射的屏蔽效应降低了截止电流（Ioff），增加了TFT的离子/离子比率，并改善了长期 在非屏蔽TFT上的TFT的阈值电压（Vt）和摆动（S）的可靠性。

公开(公告)号：US6093617A

公开(公告)日：2000-07-25

申请号：US858108

申请日：1997-05-19

申请人： Chung-Hui Su ,  Mong-Song Liang

发明人： Chung-Hui Su ,  Mong-Song Liang

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/87

摘要： A process for forming HSG polysilicon has been developed. The process features initially depositing an amorphous silicon layer, at a temperature between about 490 to 550.degree. C. The amorphous silicon layer is then subjected to an in situ anneal procedure, at a temperature between about 600 to 650.degree. C., and at a pressure between about 0.5 to 1.5 mTorr, for about 30 min, to convert the amorphous silicon layer to a HSG polysilicon layer. The surface roughness of the HSG polysilicon, when used as the top layer of a storage node structure, of a stacked capacitor structure, results in a surface area increase of about 50%, thus offering increases in capacitance.

摘要翻译： 已经开发了形成HSG多晶硅的工艺。 该工艺特征最初在约490至550℃的温度下沉积非晶硅层。然后在约600至650℃的温度和非晶硅层之间对非晶硅层进行原位退火工艺， 压力在约0.5至1.5mTorr之间约30分钟，以将非晶硅层转化为HSG多晶硅层。 当用作叠层电容器结构的存储节点结构的顶层时，HSG多晶硅的表面粗糙度导致约50％的表面积增加，从而提高了电容。