公开(公告)号：US6001731A

公开(公告)日：1999-12-14

申请号：US682457

申请日：1996-07-17

申请人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

发明人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76819 ,  H01L21/31053

摘要： A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.

摘要翻译： 一种用于提供用于防止多晶硅和多金属级电短路的化学机械抛光平面化工艺的方法，其中简要地描述了以下顺序的处理步骤：i）在具有非平面表面的器件晶片上提供第一厚度的绝缘层 地形; ii）化学机械抛光第一绝缘层; 以及iii）沉积第二厚度的另一多晶硅层，以防止几乎暴露或暴露的下面的多晶硅短路到下一个多晶硅或金属互连级。

公开(公告)号：US5652174A

公开(公告)日：1997-07-29

申请号：US650696

申请日：1996-05-20

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A method is provide for a unified stacked contact structure which concurrently forms all the polysilicon interconnects and the polysilicon load resistors on a SRAM device. FETs formed from a first polysilicon layer are coated with a first insulating layer. A second polysilicon layer is deposited and patterned forming portions of the SRAM circuit and concurrently forming openings over FET source/drain areas. A second insulating layer is deposited, and contact openings are selectively etched in the insulating layer over the openings in the second polysilicon layer. The exposed second polysilicon layer in the contacts serve as an etch mask for etching the first insulating layer to the source/drain contact areas, thereby forming contacts self-aligned to the openings in the second polysilicon layer. The contact openings in the node contact areas also expose portions of the gate electrodes .of the SRAM driver transistors. The unified stacked contacts are completed by depositing and patterning a conformal third polysilicon layer that forms interconnections in the contact openings between the exposed patterned polysilicon layers, and the third polysilicon layer is also patterned to form the polysilicon load resistors. The number of masking and other process steps are substantially reduced.

摘要翻译： 提供了一种统一的堆叠接触结构的方法，其同时形成SRAM器件上的所有多晶硅互连和多晶硅负载电阻。 由第一多晶硅层形成的FET被涂覆有第一绝缘层。 沉积第二多晶硅层并构图形成SRAM电路的部分，同时在FET源极/漏极区域上形成开口。 沉积第二绝缘层，并且在第二多晶硅层中的开口上的绝缘层中选择性地蚀刻接触开口。 触点中暴露的第二多晶硅层用作蚀刻掩模，用于将第一绝缘层蚀刻到源极/漏极接触区域，从而形成与第二多晶硅层中的开口自对准的触点。 节点接触区域中的接触开口也暴露SRAM驱动晶体管的栅电极的部分。 通过沉积和图案化形成在曝光的图案化多晶硅层之间的接触开口中形成互连的共形第三多晶硅层，并且第三多晶硅层也被图案化以形成多晶硅负载电阻来完成统一的堆叠接触。 掩模和其他工艺步骤的数量显着减少。

公开(公告)号：US5867087A

公开(公告)日：1999-02-02

申请号：US791119

申请日：1997-01-30

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

IPC分类号： H01L21/02 ,  H01C1/012

CPC分类号： H01L28/20 ,  Y10T29/49082 ,  Y10T29/49099

摘要： A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

摘要翻译： 一种三维多晶硅电阻器和制造三维多晶硅电阻器的方法。 半导体衬底在其表面上形成绝缘层。 绝缘层具有至少部分地通过绝缘层形成的至少一个孔。 在绝缘层上形成多晶硅层，并保形地形成绝缘层内的孔。 然后对多晶硅层进行构图以形成电阻器，该电阻器包括驻留在孔内的多晶硅层的部分。

公开(公告)号：US5716881A

公开(公告)日：1998-02-10

申请号：US623243

申请日：1996-03-28

申请人： Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang ,  Chung-Hui Su

发明人： Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang ,  Chung-Hui Su

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/11

CPC分类号： H01L27/10844 ,  H01L27/1052 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/105 ,  Y10S257/903

摘要： A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.

摘要翻译： 已经开发了用于集成堆叠电容器，DRAM器件和薄膜晶体管SRAM器件的制造工艺。 该制造工艺具有组合用于产生传输门晶体管结构的关键操作的特征，以及用于DRAM和SRAM器件的存取晶体管结构。 此外，用于为SRAM器件创建用于DRAM器件的电容器结构和薄膜晶体管结构的工艺步骤也被共享。 本发明的另一个关键特征是用于SRAM器件的掩埋接触结构。

公开(公告)号：US5534451A

公开(公告)日：1996-07-09

申请号：US429728

申请日：1995-04-27

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L21/285 ,  H01L23/485 ,  H01L27/11 ,  H01L29/45 ,  H01L21/283 ,  H01L21/335

CPC分类号： H01L27/1108 ,  H01L21/28512 ,  H01L23/485 ,  H01L29/458 ,  H01L2924/0002 ,  Y10S257/903

摘要： A method for fabricating reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The method involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The method provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The method further allows large latitude in etching the contact opening and thereby provides a very manufacturable process.

摘要翻译： 实现了将薄区域金属触点制造成具有低欧姆电阻的薄多晶硅层接触结构的方法。 该方法包括在由厚多晶硅层构成的缓冲层上形成绝缘层中的接触开口。 开口中的侧壁的一部分包括形成半导体器件的一部分并且还形成与金属接触件的电连接的图案化的多晶硅层。 该方法提供具有非常低的电阻和减小的面积的金属接触以增加器件封装密度。 金属接触结构也消除了形成通常与P + / N +堆叠接触相关联的P + / N +非欧姆结的问题。 该方法进一步允许蚀刻接触开口的大的纬度，从而提供非常可制造的工艺。

公开(公告)号：US5607879A

公开(公告)日：1997-03-04

申请号：US496019

申请日：1995-06-28

申请人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

公开(公告)号：US5587696A

公开(公告)日：1996-12-24

申请号：US496018

申请日：1995-06-28

申请人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

发明人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

IPC分类号： H01L21/02 ,  H01C1/012

CPC分类号： H01L28/20 ,  Y10T29/49082

摘要： A multi-layer polysilicon resistor and a method by which the multi-layer polysilicon resistor is formed. A minimum of two polysilicon layers is formed upon an insulating layer, the insulating layer in turn being formed upon a semiconductor substrate. The first polysilicon layer is formed to a first thickness at a first deposition temperature. The second polysilicon layer is formed directly upon the first polysilicon layer. The second polysilicon layer is formed to a second thickness at a second deposition temperature. The two deposition temperatures are in the range of about 450 degrees centigrade to about 620 degrees centigrade, and the difference in temperature between the first deposition temperature and the second deposition temperature is a minimum of 10 degrees centigrade.

摘要翻译： 多层多晶硅电阻器和形成多层多晶硅电阻器的方法。 在绝缘层上形成至少两个多晶硅层，绝缘层依次形成在半导体衬底上。 第一多晶硅层在第一沉积温度下形成第一厚度。 第二多晶硅层直接形成在第一多晶硅层上。 第二多晶硅层在第二沉积温度下形成第二厚度。 两个沉积温度在约450摄氏度至约620摄氏度的范围内，并且第一沉积温度和第二沉积温度之间的温度差最小为10摄氏度。

公开(公告)号：US06218286B1

公开(公告)日：2001-04-17

申请号：US09395286

申请日：1999-09-13

申请人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

发明人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76819 ,  H01L21/31053

摘要： A method of providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.

摘要翻译： 提供用于防止多晶硅和多金属级电短路的化学机械抛光平坦化工艺的方法，其中简要地描述了顺序处理步骤，i）在具有非平面表面的器件晶片上提供第一厚度的绝缘层 地形; ii）化学机械抛光第一绝缘层; 以及iii）沉积第二厚度的另一多晶硅层，以防止几乎暴露或暴露的下面的多晶硅短路到下一个多晶硅或金属互连级。

公开(公告)号：US5576243A

公开(公告)日：1996-11-19

申请号：US629253

申请日：1996-04-08

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L27/1108 ,  Y10S148/02

摘要： A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (I.sub.on) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate. The process for the plug structure also reduces the mask set by one masking level over the prior art process.

摘要翻译： 实现了一种用于制造用于低电阻欧姆堆叠触点的新型插头结构并同时与SRAM单元上的器件形成金属触点的方法。 该方法包括在堆叠的接触开口中形成导电插塞以在P +掺杂多晶硅层和N +掺杂多晶硅层之间形成欧姆连接，从而增加SRAM单元的导通电流（Ion）。 导电插塞也同时形成在金属接触开口中，到基片上别处的器件区域。 插塞结构的过程还减少了相对于现有技术方法由一个掩蔽级别设置的掩模。

公开(公告)号：US06222214B1

公开(公告)日：2001-04-24

申请号：US08630111

申请日：1996-04-08

申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

IPC分类号： H01L27108

CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L27/1108 ,  Y10S148/02

摘要： A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (Ion) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate. The process for the plug structure also reduces the mask set by one masking level over the prior art process.

摘要翻译： 实现了一种用于制造用于低电阻欧姆堆叠触点的新型插头结构并同时与SRAM单元上的器件形成金属触点的方法。 该方法包括在堆叠的接触开口中形成导电插塞以在P +掺杂多晶硅层和N +掺杂多晶硅层之间形成欧姆连接，从而增加SRAM单元的导通电流（Ion）。 导电插塞也同时形成在金属接触开口中，到基片上别处的器件区域。 插塞结构的过程还减少了相对于现有技术方法由一个掩蔽级别设置的掩模。