公开(公告)号：US11776865B2

公开(公告)日：2023-10-03

申请号：US16997767

申请日：2020-08-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Teiji Yamamoto ,  Masayuki Aoike ,  Hiroyuki Nagai

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3121 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/13 ,  H01L25/0652 ,  H01L2223/6644

Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.

公开(公告)号：US11677018B2

公开(公告)日：2023-06-13

申请号：US16901980

申请日：2020-06-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike

IPC: H01L23/373 ,  H01L29/737 ,  H01L23/00 ,  H01L23/498 ,  H01L21/50

CPC classification number: H01L29/737 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/14

Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.

公开(公告)号：US10985123B2

公开(公告)日：2021-04-20

申请号：US16751899

申请日：2020-01-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Masayuki Aoike ,  Takayuki Tsutsui

IPC: H01L23/00 ,  H01L27/088 ,  H01L29/165 ,  H01L29/205 ,  H01L29/737 ,  H01L27/082 ,  H01L21/8234 ,  H01L21/8222 ,  H03F3/213 ,  H03F3/195

Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

公开(公告)号：US10396148B2

公开(公告)日：2019-08-27

申请号：US15960845

申请日：2018-04-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/76 ,  H01L21/762 ,  H01L29/47 ,  H01L29/205

Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.

公开(公告)号：US20180108589A1

公开(公告)日：2018-04-19

申请号：US15784667

申请日：2017-10-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike ,  Atsushi Kurokawa ,  Atsushi Kobayashi

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/02

CPC classification number: H01L23/3192 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.

公开(公告)号：US12278425B2

公开(公告)日：2025-04-15

申请号：US18308315

申请日：2023-04-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takanori Uejima ,  Yuji Takematsu ,  Yukiya Yamaguchi ,  Shunji Yoshimi ,  Satoshi Arayashiki ,  Mitsunori Samata ,  Satoshi Goto ,  Yutaka Sasaki ,  Masayuki Aoike

IPC: H01Q1/42 ,  H01Q1/22 ,  H01Q1/38 ,  H03H3/02

Abstract: A radio-frequency module includes a first base made of a first semiconductor material; a second base that is made of a second semiconductor material having a thermal conductivity lower than that of the first semiconductor material and which includes a power amplifier circuit; a third base including a transmission filter circuit; and a module substrate having a main surface on which the first base, the second base, and the third base are arranged. The first base is joined to the main surface via an electrode. The second base is arranged between the module substrate and the first base in a sectional view and is joined to the main surface via an electrode. At least part of the first base is overlapped with at least part of the second base and at least part of the third base in a plan view.

公开(公告)号：US12199083B2

公开(公告)日：2025-01-14

申请号：US18459248

申请日：2023-08-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H03F1/56 ,  H03F3/195

Abstract: An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.

公开(公告)号：US11804450B2

公开(公告)日：2023-10-31

申请号：US17644043

申请日：2021-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi Goto ,  Masayuki Aoike ,  Mikiko Fukasawa

IPC: H01L23/552 ,  H01L23/49 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49822 ,  H01L24/24 ,  H01L24/94 ,  H01L24/97 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05569 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/24146 ,  H01L2224/4813 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10329

Abstract: A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.

公开(公告)号：US20230299726A1

公开(公告)日：2023-09-21

申请号：US18166369

申请日：2023-02-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi Goto ,  Masayuki Aoike ,  Takayuki Tsutsui ,  Kenji Sasaki

IPC: H03F3/195 ,  H01L23/66 ,  H03F3/24 ,  H03F1/02 ,  H03F1/56

CPC classification number: H03F3/195 ,  H01L23/66 ,  H03F1/0288 ,  H03F1/565 ,  H03F3/245 ,  H01L2223/6611 ,  H01L2223/6655 ,  H03F2200/451

Abstract: A semiconductor device includes first and second members. A second surface of the second member is opposite to a first surface of the first member. A radio-frequency amplifier circuit is included in the second member. The first and second members are bonded to each other by an electrically conductive bonding member between the first and second surfaces. The radio-frequency amplifier circuit includes at least one power stage transistor, an input wire that is connected to the power stage transistor and supplies an input signal to the power stage transistor, and an input-side circuit element that is connected to the input wire and that includes at least one of a passive element, an active element, and an external connection terminal. The bonding member includes a first conductor pattern covering the power stage transistor in plan view. The input-side circuit element is disposed outside the first conductor pattern in plan view.

公开(公告)号：US11728235B2

公开(公告)日：2023-08-15

申请号：US16997767

申请日：2020-08-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Teiji Yamamoto ,  Masayuki Aoike ,  Hiroyuki Nagai

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3121 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/13 ,  H01L25/0652 ,  H01L2223/6644

Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.