公开(公告)号：US10163749B2

公开(公告)日：2018-12-25

申请号：US15784709

申请日：2017-10-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike ,  Atsushi Kurokawa ,  Atsushi Kobayashi

IPC: H01L23/31 ,  H01L21/02

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.

公开(公告)号：US20180108588A1

公开(公告)日：2018-04-19

申请号：US15784709

申请日：2017-10-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike ,  Atsushi Kurokawa ,  Atsushi Kobayashi

IPC: H01L23/31 ,  H01L21/02

CPC classification number: H01L23/3171 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L23/3192 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.

公开(公告)号：US12262556B2

公开(公告)日：2025-03-25

申请号：US17549566

申请日：2021-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shaojun Ma ,  Shigeki Koya ,  Masayuki Aoike ,  Shinnosuke Takahashi ,  Yasunari Umemoto ,  Masatoshi Hase

IPC: H01L29/737 ,  H01L29/423 ,  H03F3/217 ,  H10D10/80 ,  H10D64/00 ,  H10D64/23 ,  H10D64/27 ,  H10D64/60

Abstract: A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

公开(公告)号：US12136664B2

公开(公告)日：2024-11-05

申请号：US18296778

申请日：2023-04-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike

IPC: H01L23/373 ,  H01L21/50 ,  H01L23/00 ,  H01L23/498 ,  H01L29/737

Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.

公开(公告)号：US10157812B2

公开(公告)日：2018-12-18

申请号：US15784667

申请日：2017-10-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike ,  Atsushi Kurokawa ,  Atsushi Kobayashi

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/29 ,  H01L21/02 ,  H01L21/285 ,  H01L21/288

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.

公开(公告)号：US12009359B2

公开(公告)日：2024-06-11

申请号：US17504269

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike ,  Takayuki Tsutsui ,  Shigeki Koya

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L27/02 ,  H01L27/06 ,  H01L23/00

CPC classification number: H01L27/0658 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L2224/05644 ,  H01L2224/08 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/24146

Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

公开(公告)号：US11764197B2

公开(公告)日：2023-09-19

申请号：US17196965

申请日：2021-03-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki Aoike

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H03F1/56 ,  H03F3/195

CPC classification number: H01L25/18 ,  H01L23/367 ,  H01L24/16 ,  H01L24/48 ,  H01L25/50 ,  H03F1/56 ,  H03F3/195 ,  H01L2224/16227 ,  H01L2224/48145 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate.

公开(公告)号：US11145607B2

公开(公告)日：2021-10-12

申请号：US16838977

申请日：2020-04-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yusuke Tanaka ,  Fumio Harima ,  Masayuki Aoike ,  Koshi Himeda

IPC: H01L23/58 ,  H01L23/66 ,  H01L23/00

Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.

公开(公告)号：US10734310B2

公开(公告)日：2020-08-04

申请号：US16210135

申请日：2018-12-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Masayuki Aoike ,  Takayuki Tsutsui

IPC: H01L23/49 ,  H01L23/14 ,  H01L23/29 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

Abstract: A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors.

公开(公告)号：US11876032B2

公开(公告)日：2024-01-16

申请号：US17504316

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike ,  Masatoshi Hase ,  Fumio Harima

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L29/737

CPC classification number: H01L23/3738 ,  H01L23/3736 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/24 ,  H01L29/7371 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/24146

Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.