公开(公告)号：US20140145294A1

公开(公告)日：2014-05-29

申请号：US13687110

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Sascha Moeller ,  Martin Lapke

IPC: H01L27/04 ,  H01L21/78

CPC classification number: H01L21/78

Abstract: A method is provided for separation of a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes. The lanes are located between the ICs and extend between a front-side of the metallization layers and a backside of the substrate. A backside of the substrate is thinned, and laser pulses are applied via the backside of the substrate to change the crystalline structure of the silicon substrate along the lanes. The plurality of portions in the silicon substrate and the channels are configured to propagate cracks in the silicon substrate along the lanes during expansion of the IC wafer. The channels assist to mitigate propagation of cracks outside of the lanes in the metallization layers during expansion of the IC wafer.

Abstract translation: 提供了一种用于将晶片分离成单个IC的方法。 通道沿着各个通道形成在晶片前侧上的一个或多个金属化层中。 通道位于IC之间并且在金属化层的前侧和衬底的背面之间延伸。 衬底的背面变薄，并且通过衬底的背面施加激光脉冲以沿着通道改变硅衬底的晶体结构。 硅衬底和通道中的多个部分被配置为在IC晶片的膨胀期间沿着通道在硅衬底中传播裂纹。 在IC晶片的膨胀期间，通道有助于减轻在金属化层中的通道外的裂纹的传播。

公开(公告)号：US09847258B2

公开(公告)日：2017-12-19

申请号：US14871482

申请日：2015-09-30

Applicant: NXP B.V.

Inventor： Thomas Rohleder ,  Hartmut Buenning ,  Guido Albermann ,  Sascha Moeller ,  Martin Lapke

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/311 ,  H01L21/66 ,  H01L27/04 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/12 ,  H01L23/528 ,  H01L27/04

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

公开(公告)号：US09349645B2

公开(公告)日：2016-05-24

申请号：US14055188

申请日：2013-10-16

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Heiko Backer

IPC: H01L21/00 ,  H01L21/78 ,  B28D5/00 ,  B28D1/22 ,  H01L21/683 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/78 ,  B28D1/221 ,  B28D5/0041 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  Y10T225/287 ,  Y10T225/298

Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.

Abstract translation: 公开了一种用于晶片切割的装置，装置和方法。 在一个示例中，该装置公开了：具有第一温度的晶片保持装置; 可移动地联接到晶片保持装置的模具分离杆; 以及联接到所述设备并具有第二温度的冷却装置，其使得能够使所述模具分离杆响应于相对于所述晶片保持装置的运动而破坏附着材料。 在另一示例中，该方法公开了：接收具有施加到晶片一侧的附着材料的晶片; 将晶片放置在具有第一温度的保持装置中; 推动模具分离杆朝向晶片; 并将附着材料冷却至低于第一温度的第二温度，直到附着材料响应于推动而断裂。

公开(公告)号：US20160071770A1

公开(公告)日：2016-03-10

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/306 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

Abstract translation: 与示例性实施例一致，从具有有源器件和背面的正面的晶片衬底制备集成电路（IC）器件管芯的方法包括将晶片的前侧安装到保护箔上。 在第一聚焦深度处将激光施加到晶片背面上的锯道区域以限定修改区域; 修改区域在活动设备边界内的预定深度和由锯道区域限定的活动设备边界中定义。 保护箔被拉伸以将IC器件管芯彼此分开并暴露有源器件侧壁。 通过对有源器件侧壁的干蚀刻，基本上去除了改质区。

公开(公告)号：US09196537B2

公开(公告)日：2015-11-24

申请号：US13967164

申请日：2013-08-14

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth Van Gemert ,  Hartmut Buenning ,  Tonny Kamphuis ,  Sascha Moeller ,  Christian Zenz

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/782 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

Abstract translation: 与示例性实施例一致，存在用于组装晶片级芯片尺寸处理（WLCSP）晶片的方法; 晶片具有顶侧表面和背面表面，以及在顶侧表面上具有电触头的多个器件裸片。 该方法包括对晶片的背面进行背面研磨至厚度。 在晶片的背面上模制厚度保护层。 将晶片安装在锯片上; 沿着多个器件裸片的锯条，晶片被锯切，锯切发生在第一切口的刀片和背面晶片厚度的深度上。 再次，晶片沿着多个器件裸片的锯条被锯切，锯切发生在第二切口的刀片上，第二切口比第一切口窄，并锯切到保护层厚度的深度。 将多个器件裸片分离为单个器件管芯。 每个单独的器件管芯在背面具有保护层，保护层具有与单独器件管芯的垂直边缘的间隔距离。

公开(公告)号：US08895363B2

公开(公告)日：2014-11-25

申请号：US13833906

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Michael Zernack

IPC: H01L21/44 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.

Abstract translation: 与示例性实施例一致，存在从晶片衬底组装晶片级芯片级处理（WLCSP）器件的方法，该方法包括将晶片衬底的背面磨削至规定厚度。 多个沟槽沿着晶片的背面表面上的多个器件裸片边界锯切，沟槽具有斜面形状。 多个沟槽被蚀刻直到多个沟槽的斜面轮廓为圆形。