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    FRINGE CAPACITOR ARRANGED BASED ON METAL LAYERS WITH A SELECTED ORIENTATION OF A PREFERRED DIRECTION
    14.
    发明申请
    FRINGE CAPACITOR ARRANGED BASED ON METAL LAYERS WITH A SELECTED ORIENTATION OF A PREFERRED DIRECTION 有权

    公开(公告)号：US20220344257A1

    公开(公告)日：2022-10-27

    申请号：US17239884

    申请日：2021-04-26

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Bartholomeus Wilhelmus Christiaan Hovens ,  Marina Vroubel

    IPC: H01L23/522 ,  H01L49/02

    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor

    Semiconductor device comprising a PN junction diode
    15.
    发明授权
    Semiconductor device comprising a PN junction diode 有权

    公开(公告)号：US10580906B1

    公开(公告)日：2020-03-03

    申请号：US16148285

    申请日：2018-10-01

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Marina Vroubel ,  Paul Alexander Grudowski

    IPC: H01L29/861 ,  H01L29/417 ,  H01L27/02 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

    Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.

    FIELD EFFECT TRANSISTOR AND METHOD OF MAKING
    16.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF MAKING 审中-公开

    公开(公告)号：US20190181234A1

    公开(公告)日：2019-06-13

    申请号：US15840622

    申请日：2017-12-13

    Applicant: NXP B.V.

    Inventor： Lukas Frederik Tiemeijer ,  Viet Thanh Dinh ,  Valerie Marthe Girault

    IPC: H01L29/417 ,  H01L23/66 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L29/41758 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/66 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/785

    Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.

    Bipolar Transistor
    18.
    发明申请
    Bipolar Transistor 有权
    双极晶体管

    公开(公告)号：US20160079345A1

    公开(公告)日：2016-03-17

    申请号：US14852385

    申请日：2015-09-11

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee ,  Ponky Ivo ,  Dirk Klaassen ,  Mahmoud Shehab Mohammad Al-Sa'di

    IPC: H01L29/06 ,  H01L29/66 ,  H03F3/21 ,  H01L29/417 ,  H01L21/324 ,  H01L29/735 ,  H01L29/08

    CPC classification number: H01L29/063 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378 ,  H03F3/21

    Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

    Abstract translation: 一种包括双极晶体管的半导体器件及其制造方法。 一种功率放大器，包括双极晶体管。 双极晶体管包括具有横向延伸漂移区的集电极。 双极晶体管还包括位于集电极之上的基极。 双极晶体管还包括位于基极上方的发射极。 双极晶体管还包括具有不同于集电极的导电类型的掺杂区域。 掺杂区域在集电极下方横向延伸以在掺杂区域和集电极之间的接触区域处形成结。 掺杂区域具有非均匀的横向掺杂分布。 在最接近双极晶体管的集电极 - 基极结的掺杂区域的一部分中，掺杂区域的掺杂水平最高。

    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT
    19.
    发明申请
    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT 审中-公开
    晶体管放大器电路和集成电路

    公开(公告)号：US20150145005A1

    公开(公告)日：2015-05-28

    申请号：US14542990

    申请日：2014-11-17

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Tony Vanhoucke ,  Evelyne Gridelet ,  Anco Heringa ,  Jan Willem Slotboom ,  Dirk Klaassen

    IPC: H01L29/737 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

    CPC classification number: H01L29/7371 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/735 ,  H01L29/7378 ,  H01L29/7809 ,  H01L29/7835

    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

    Abstract translation: 公开了具有第一导电类型的第一区域用于将电荷载体注入晶体管的第一区域和第二导电类型的横向延伸的第二区域的晶体管，其具有包括用于从晶体管排出所述电荷载流子的接触端子的部分，其中， 第一区域与第二区域通过限定与第一区域的第一pn结的第二导电类型的中间区域和与第二区域的第二pn结分离，其中横向延伸区域将第二pn结部分与第二pn结分离， 并且其中所述晶体管还包括具有所述第二导电类型的掺杂区域的衬底，所述掺杂区域沿着所述横向延伸的第二区域接触并延伸，以及另外的接触端子，其连接到所述掺杂区域，以从所述掺杂区域中排出少数电荷载流子 横向延伸的第二区域。 还公开了包括这种晶体管的放大器电路和IC。

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