公开(公告)号：US06617894B2

公开(公告)日：2003-09-09

申请号：US10081359

申请日：2002-02-20

Applicant: Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

Inventor： Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

IPC: H03L700

CPC classification number: G06F1/10 ,  H03K5/135

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

公开(公告)号：US6114885A

公开(公告)日：2000-09-05

申请号：US138641

申请日：1998-08-24

Applicant: Seung-Kweon Yang ,  Yong-Jin Yoon

Inventor： Seung-Kweon Yang ,  Yong-Jin Yoon

IPC: G11C11/417 ,  H03H11/28 ,  H03K19/00 ,  H03K3/00

CPC classification number: H03K19/0005

Abstract: Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal. Moreover, the first variable resistance device and the second variable resistance device may be external to the pull-up circuit and the pull-up circuit, respectively. The resistances of the first and second variable resistance devices may also be independently controllable as separate potentiometers.

Abstract translation: 集成驱动器电路包括其中具有第一多个PMOS上拉晶体管的上拉电路，其被第一多位阻抗控制信号选择性地使能。 该第一多位阻抗控制信号是第一可变电阻装置的功能。 还提供了一个下拉电路。 下拉电路具有其中的第一多个NMOS下拉晶体管，其被第二多位阻抗控制信号选择性地使能。 该第二多位阻抗控制信号是第二可变电阻装置的电阻的函数。 上拉电路和下拉电路具有共同连接的输出。 特别地，上拉电路具有第一阻抗，其是第一多位阻抗控制信号的数字值的函数，并且下拉电路具有作为第二多位阻抗控制信号的数字值的函数的第二阻抗 多位阻抗控制信号。 此外，第一可变电阻装置和第二可变电阻装置可以分别在上拉电路和上拉电路的外部。 第一和第二可变电阻器件的电阻也可独立地作为单独的电位计来控制。

公开(公告)号：US20120319753A1

公开(公告)日：2012-12-20

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03L7/00

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。

公开(公告)号：US07295489B2

公开(公告)日：2007-11-13

申请号：US11037602

申请日：2005-01-18

Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

公开(公告)号：US08643420B2

公开(公告)日：2014-02-04

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。

公开(公告)号：US08578227B2

公开(公告)日：2013-11-05

申请号：US12944787

申请日：2010-11-12

Applicant: Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G06F11/24

Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Abstract translation: 用于片上系统的测试装置包括顺序逻辑电路和测试电路。 顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于 串行时钟信号和串行使能信号。 测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试 和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

公开(公告)号：US20050157827A1

公开(公告)日：2005-07-21

申请号：US11037602

申请日：2005-01-18

Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/40 ,  H04L7/00

CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

公开(公告)号：US6115298A

公开(公告)日：2000-09-05

申请号：US223174

申请日：1998-12-30

Applicant: Ig-Soo Kwon ,  Yong-Jin Yoon

Inventor： Ig-Soo Kwon ,  Yong-Jin Yoon

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/34 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  G11C7/00

CPC classification number: G11C7/1048

Abstract: A semiconductor device connected to a bus consisting of a plurality of signal lines, comprises a first pad connected with a discrete resistor corresponding to the impedance of the signal lines, a plurality of second pads respectively connected with the signal lines, a reference voltage generator for generating a reference voltage, a comparator for comparing the voltage on the first pad with the reference voltage to generate a control signal, a code generator for generating a code signal according to the control signal, a current source for supplying the first pad with variable current according to the code signal, and a data driver for driving data signals to the signal lines connected with the second pads according to the code signal. The code signal is used to match the impedance of the data driver with the impedance of the signal lines.

Abstract translation: 连接到由多个信号线组成的总线的半导体器件包括与分立电阻器相连的第一焊盘，该分立电阻器对应于信号线的阻抗，多个分别与信号线连接的第二焊盘，参考电压发生器， 产生参考电压，比较器，用于将第一焊盘上的电压与参考电压进行比较以产生控制信号;代码发生器，用于根据控制信号产生代码信号;电流源，用于向第一焊盘提供可变电流 以及数据驱动器，用于根据代码信号向与第二焊盘相连的信号线驱动数据信号。 代码信号用于将数据驱动器的阻抗与信号线的阻抗相匹配。