公开(公告)号：US6115298A

公开(公告)日：2000-09-05

申请号：US223174

申请日：1998-12-30

Applicant: Ig-Soo Kwon ,  Yong-Jin Yoon

Inventor： Ig-Soo Kwon ,  Yong-Jin Yoon

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/34 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  G11C7/00

CPC classification number: G11C7/1048

Abstract: A semiconductor device connected to a bus consisting of a plurality of signal lines, comprises a first pad connected with a discrete resistor corresponding to the impedance of the signal lines, a plurality of second pads respectively connected with the signal lines, a reference voltage generator for generating a reference voltage, a comparator for comparing the voltage on the first pad with the reference voltage to generate a control signal, a code generator for generating a code signal according to the control signal, a current source for supplying the first pad with variable current according to the code signal, and a data driver for driving data signals to the signal lines connected with the second pads according to the code signal. The code signal is used to match the impedance of the data driver with the impedance of the signal lines.

Abstract translation: 连接到由多个信号线组成的总线的半导体器件包括与分立电阻器相连的第一焊盘，该分立电阻器对应于信号线的阻抗，多个分别与信号线连接的第二焊盘，参考电压发生器， 产生参考电压，比较器，用于将第一焊盘上的电压与参考电压进行比较以产生控制信号;代码发生器，用于根据控制信号产生代码信号;电流源，用于向第一焊盘提供可变电流 以及数据驱动器，用于根据代码信号向与第二焊盘相连的信号线驱动数据信号。 代码信号用于将数据驱动器的阻抗与信号线的阻抗相匹配。

公开(公告)号：US07016257B2

公开(公告)日：2006-03-21

申请号：US10790262

申请日：2004-03-01

Applicant: Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

Inventor： Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

IPC: G11C8/00

CPC classification number: G11C29/12015 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C29/14

Abstract: A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode.

Abstract translation: 一种半导体存储器件，包括：存储器单元阵列; 地址输入电路，用于响应于地址时钟信号接收外部地址; 选择电路，用于响应于从地址输入电路输出的地址来选择存储单元; 数据输出电路，用于响应于第一和第二数据时钟信号输出从所选存储单元读出的数据; 以及内部时钟发生电路，用于响应于外部时钟信号及其互补时钟信号产生地址时钟信号和第一和第二数据时钟信号，其中地址时钟信号和第一和第二数据时钟信号具有两倍 在测试模式时外部时钟信号的频率（或一半周期）。

公开(公告)号：US6114885A

公开(公告)日：2000-09-05

申请号：US138641

申请日：1998-08-24

Applicant: Seung-Kweon Yang ,  Yong-Jin Yoon

Inventor： Seung-Kweon Yang ,  Yong-Jin Yoon

IPC: G11C11/417 ,  H03H11/28 ,  H03K19/00 ,  H03K3/00

CPC classification number: H03K19/0005

Abstract: Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal. Moreover, the first variable resistance device and the second variable resistance device may be external to the pull-up circuit and the pull-up circuit, respectively. The resistances of the first and second variable resistance devices may also be independently controllable as separate potentiometers.

Abstract translation: 集成驱动器电路包括其中具有第一多个PMOS上拉晶体管的上拉电路，其被第一多位阻抗控制信号选择性地使能。 该第一多位阻抗控制信号是第一可变电阻装置的功能。 还提供了一个下拉电路。 下拉电路具有其中的第一多个NMOS下拉晶体管，其被第二多位阻抗控制信号选择性地使能。 该第二多位阻抗控制信号是第二可变电阻装置的电阻的函数。 上拉电路和下拉电路具有共同连接的输出。 特别地，上拉电路具有第一阻抗，其是第一多位阻抗控制信号的数字值的函数，并且下拉电路具有作为第二多位阻抗控制信号的数字值的函数的第二阻抗 多位阻抗控制信号。 此外，第一可变电阻装置和第二可变电阻装置可以分别在上拉电路和上拉电路的外部。 第一和第二可变电阻器件的电阻也可独立地作为单独的电位计来控制。

公开(公告)号：US20120319753A1

公开(公告)日：2012-12-20

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03L7/00

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。

公开(公告)号：US20070139084A1

公开(公告)日：2007-06-21

申请号：US11627794

申请日：2007-01-26

Applicant: Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03K5/22

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US20050146365A1

公开(公告)日：2005-07-07

申请号：US11031129

申请日：2005-01-07

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G11C11/40 ,  G11C7/00 ,  G11C8/00 ,  G11C11/407 ,  H03K5/13 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K5/135

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract translation: 提供一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

公开(公告)号：US07400177B2

公开(公告)日：2008-07-15

申请号：US11627794

申请日：2007-01-26

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US07295489B2

公开(公告)日：2007-11-13

申请号：US11037602

申请日：2005-01-18

Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

公开(公告)号：US06933758B2

公开(公告)日：2005-08-23

申请号：US10308453

申请日：2002-12-03

Applicant: Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

Inventor： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC classification number: H03L7/0814 ,  H03L7/087

Abstract: A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

Abstract translation: 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

公开(公告)号：US08643420B2

公开(公告)日：2014-02-04

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。