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18 条记录 (耗时 0.025 秒)

    Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization
    11.
    发明授权
    Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization 失效
    具有增加的速度和改善的触发器利用率的多路复用的旁路存储器件

    公开(公告)号：US5570051A

    公开(公告)日：1996-10-29

    申请号：US454908

    申请日：1995-05-31

    申请人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

    发明人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

    IPC分类号： H03K19/173 ,  H03K3/037 ,  H03K19/177 ,  H03K3/289

    CPC分类号： H03K19/17732 ,  H03K19/17704

    摘要： A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

    摘要翻译： 可以通过使用多路复用时钟和高效的器件设计和增强的触发器利用来实现具有增加的存储速度和增强的存储器利用率的存储器件。 可以通过多路复用的时钟信号来控制通过电路的传输时间，从而可以控制电路速度，并通过在信号路径中使用更少的晶体管来增加数据，并通过旁路触发器的主器件将数据直接传输到触发器输出 锁存输入。

    Low-power memory device with accelerated sense amplifiers
    12.
    发明授权
    Low-power memory device with accelerated sense amplifiers 失效
    具有加速读出放大器的低功耗存储器件

    公开(公告)号：US5526322A

    公开(公告)日：1996-06-11

    申请号：US311094

    申请日：1994-09-23

    申请人： Napoleon W. Lee

    发明人： Napoleon W. Lee

    IPC分类号： G11C16/26 ,  G11C13/00 ,  G11C7/00

    CPC分类号： G11C16/26

    摘要： An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

    摘要翻译： 用于可擦除可编程逻辑器件（EPLD）的AND阵列包括用于指示从高到低的字线转换的字线转换检测器。 这种转换是低到高位线转换的先决条件。 转换指示由快速转换检测读出放大器缓冲，其输出被提供给读出AND阵列的位线的多个“可模式切换”读出放大器中的每一个。 每个可切换模式的读出放大器将转换指示与其自己的输出逻辑组合，以选择其工作模式。 只有当转换指示有效且读出放大器的当前输出为低电平时，才输入快速（强源电流）模式。 否则，大多数时候，模式切换读出放大器保持低功耗（弱电流）模式。 这种布置提供了具有较低时间平均功率消耗的较高速度运行。

    Power-on reset circuit including dual sense amplifiers
    13.
    发明授权
    Power-on reset circuit including dual sense amplifiers 失效
    上电复位电路包括双重放大器

    公开(公告)号：US5394104A

    公开(公告)日：1995-02-28

    申请号：US293782

    申请日：1994-08-22

    申请人： Napoleon W. Lee

    发明人： Napoleon W. Lee

    IPC分类号： H03K3/3565 ,  H03K17/22 ,  H03L7/00

    CPC分类号： H03K17/223 ,  H03K17/22 ,  H03K3/3565

    摘要： A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

    摘要翻译： 提供上电复位电路，其将集成电路器件保持在复位模式，直到满足至少两个条件：电源电压Vcc必须高于指定值，并且器件中的读出放大器必须能够正常工作。 延迟电路和施密特触发电路还可以提高将器件从其复位模式释放的信号的稳定性。

    Configurable performance-optimized programmable logic device
    14.
    发明授权
    Configurable performance-optimized programmable logic device 失效
    可配置性能优化的可编程逻辑器件

    公开(公告)号：US5801548A

    公开(公告)日：1998-09-01

    申请号：US630321

    申请日：1996-04-11

    申请人： Napoleon W. Lee ,  Derek R. Curd

    发明人： Napoleon W. Lee ,  Derek R. Curd

    IPC分类号： H03K19/00 ,  H03K19/0185

    CPC分类号： H03K19/0027

    摘要： A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

    摘要翻译： 一种可编程逻辑器件（PLD），包括用于在生产后改变PLD的速度 - 功率特性的可配置电路，并允许PLD选择性地在3.3伏或5伏电源上工作。 可配置电路包括输入缓冲器，输出缓冲器和参考发生器。 输入缓冲器包括与专用N沟道晶体管串联连接的专用P沟道晶体管，以及选择性地与专用晶体管并联的多个跳变点调整晶体管，以调整输入缓冲器的跳变点 通过改变N对P比例。 输出缓冲器包括两个可配置的缓冲器，其跳变点也可调。 还提供了可配置的参考发生器，用于产生高精度参考电压，其被提供给位于PLD的功能块和互连矩阵中的读出放大器。

    Efficient in-system programming structure and method for non-volatile programmable logic devices
    15.
    发明授权
    Efficient in-system programming structure and method for non-volatile programmable logic devices 失效
    用于非易失性可编程逻辑器件的高效的在系统编程结构和方法

    公开(公告)号：US5734868A

    公开(公告)日：1998-03-31

    申请号：US512796

    申请日：1995-08-09

    申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

    发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

    IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  H03K19/77

    CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

    摘要： An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

    摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

    Power saving sense amplifier that mimics non-toggling bitline states
    17.
    发明授权
    Power saving sense amplifier that mimics non-toggling bitline states 失效
    省电读出放大器，模拟非切换位线状态

    公开(公告)号：US5524097A

    公开(公告)日：1996-06-04

    申请号：US398019

    申请日：1995-03-03

    申请人： Napoleon W. Lee

    发明人： Napoleon W. Lee

    IPC分类号： G11C16/26 ,  H03K19/177 ,  G11C7/06

    CPC分类号： G11C16/26 ,  H03K19/17712

    摘要： A sense amplifier of the present invention provides power savings of between 30% to 70% for typical usage of a programmable logic device. In one embodiment, this sense amplifier includes circuitry for detecting and propagating the logic state on a bit line, an amplifier for amplifying the propagated logic state, and configuration logic for receiving a first configuration bit and a second configuration bit. If the first configuration bit and the second configuration bit have different logic states (indicating a non-toggling state), then the sense amplifier mimics the bit line at either a first logic state or a second logic state. Specifically, if the first configuration bit has the first logic state and the second configuration bit has the second logic state, then the sense amplifier mimics the bit line at the first logic state. However, if the first configuration bit has the second logic state and the second configuration bit has the first logic state, then the sense amplifier mimics the bit line at the second logic state. The sense amplifier of the present invention in its non-toggling states prevents the formation of a current branch, thereby eliminating undesirable power consumption. In contrast, if the first and second configuration bits have the same logic state (indicating a toggling state), then the sense amplifier toggles based on the change in voltage on the bit line.

    摘要翻译： 本发明的读出放大器为可编程逻辑器件的典型使用提供了30％至70％之间的功率节省。 在一个实施例中，该读出放大器包括用于检测和传播位线上的逻辑状态的电路，用于放大传播逻辑状态的放大器和用于接收第一配置位和第二配置位的配置逻辑。 如果第一配置位和第二配置位具有不同的逻辑状态（指示非切换状态），则读出放大器在第一逻辑状态或第二逻辑状态下模拟位线。 具体地说，如果第一配置位具有第一逻辑状态并且第二配置位具有第二逻辑状态，则读出放大器在第一逻辑状态模拟位线。 然而，如果第一配置位具有第二逻辑状态并且第二配置位具有第一逻辑状态，则读出放大器在第二逻辑状态模拟位线。 本发明的读出放大器在其非切换状态下阻止了电流分支的形成，从而消除了不期望的功耗。 相反，如果第一和第二配置位具有相同的逻辑状态（指示切换状态），则读出放大器基于位线上的电压变化来切换。