公开(公告)号：US5764076A

公开(公告)日：1998-06-09

申请号：US670472

申请日：1996-06-26

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17704 ,  H03K19/17756

摘要： A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

摘要翻译： 一种复杂的可编程逻辑器件（PLD），包括多个可编程功能块和用于接收编程指令的指令总线。 编程指令用于对功能块进行编程，以使PLD能够执行一个或多个所需的逻辑功能。 PLD还包括连接到每个功能块的指令阻塞电路。 当用户指示时，指令分块电路有选择地阻止来自一个或多个功能块的指令总线上的编程指令，同时允许其他功能块接收编程指令。 因此，PLD中的一个或多个功能块被重新编程，而不中断剩余功能块的操作。

公开(公告)号：US5563827A

公开(公告)日：1996-10-08

申请号：US533412

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

IPC分类号： G11C16/12 ,  G11C13/00

CPC分类号： G11C16/12

摘要： A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

摘要翻译： 具有闪存单元的集成可编程逻辑器件（PLD）中的字线的字线驱动器。 字线驱动器包括接受二进制字线输入信号的输入端子，耦合到输入端子和模式控制端子的通过栅极，以及根据通路或模式控制端子接收输入的反相器， 在PLD的操作模式下。 来自反相器的输出信号被耦合到多路复用器，该多路复用器在该输出和来自电压源的信号之间选择根据PLD的操作模式选择的信号。 复用器将所选信号输出到PLD的字线。

公开(公告)号：US5949987A

公开(公告)日：1999-09-07

申请号：US48923

申请日：1998-03-26

申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  G05B19/045

CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

摘要： An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

公开(公告)号：US5838901A

公开(公告)日：1998-11-17

申请号：US692389

申请日：1996-08-05

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F1/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

公开(公告)号：US5661685A

公开(公告)日：1997-08-26

申请号：US533131

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

IPC分类号： G11C16/02 ,  G06F17/50 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/17784 ,  G06F17/5054 ,  H03K19/17704

摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

摘要翻译： 集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。 可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

公开(公告)号：US5631583A

公开(公告)日：1997-05-20

申请号：US676992

申请日：1996-07-08

申请人： Napoleon W. Lee ,  Wei-Yi Ku

发明人： Napoleon W. Lee ,  Wei-Yi Ku

IPC分类号： G11C7/06 ,  H03F3/45

CPC分类号： G11C7/067

摘要： A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase. Thus, the present invention accelerates the low-to-high signal transition on the amplified bitline in the low power mode. If the signal on the wordline is either a constant high or low, then the additional pull-up is disabled, thereby conserving power during the low power mode. In a further aspect of the invention, a sense amplifier is provided for a cross-point interconnect matrix which avoids coupling noise by isolating the bitline from the access transistors using an EPROM cell.

摘要翻译： 根据本发明的可重构读出放大器以高切换速度模式工作，其中功耗是不太关键的考虑因素，或者在低功耗模式中，其中切换速度是不太重要的考虑因素。 在高速模式中，本发明提供了对放大位线的附加上拉，其结合现有的弱上拉仍然允许放大的位线上的信号受到位线上的电压变化的影响。 在低功率模式中，如果字线上的信号从高电平变为低电平（即指示在位线上可能发生低电平到高电平信号转换），本发明在放大的位线上提供暂时上拉。 以这种方式，本发明预期当发生这种转变时，放大的位线上的电压也可能增加。 因此，本发明在低功率模式下加速放大的位线上的低电平到高电平信号转换。 如果字线上的信号是恒定的高电平或低电平，则禁用附加上拉，从而在低功耗模式下节省功率。 在本发明的另一方面，提供了一种用于交叉点互连矩阵的读出放大器，其通过使用EPROM单元将存储晶体管与位线隔离来避免耦合噪声。

公开(公告)号：US5570051A

公开(公告)日：1996-10-29

申请号：US454908

申请日：1995-05-31

申请人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

发明人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

IPC分类号： H03K19/173 ,  H03K3/037 ,  H03K19/177 ,  H03K3/289

CPC分类号： H03K19/17732 ,  H03K19/17704

摘要： A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

摘要翻译： 可以通过使用多路复用时钟和高效的器件设计和增强的触发器利用来实现具有增加的存储速度和增强的存储器利用率的存储器件。 可以通过多路复用的时钟信号来控制通过电路的传输时间，从而可以控制电路速度，并通过在信号路径中使用更少的晶体管来增加数据，并通过旁路触发器的主器件将数据直接传输到触发器输出 锁存输入。

公开(公告)号：US5526322A

公开(公告)日：1996-06-11

申请号：US311094

申请日：1994-09-23

申请人： Napoleon W. Lee

发明人： Napoleon W. Lee

IPC分类号： G11C16/26 ,  G11C13/00 ,  G11C7/00

CPC分类号： G11C16/26

摘要： An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

摘要翻译： 用于可擦除可编程逻辑器件（EPLD）的AND阵列包括用于指示从高到低的字线转换的字线转换检测器。 这种转换是低到高位线转换的先决条件。 转换指示由快速转换检测读出放大器缓冲，其输出被提供给读出AND阵列的位线的多个“可模式切换”读出放大器中的每一个。 每个可切换模式的读出放大器将转换指示与其自己的输出逻辑组合，以选择其工作模式。 只有当转换指示有效且读出放大器的当前输出为低电平时，才输入快速（强源电流）模式。 否则，大多数时候，模式切换读出放大器保持低功耗（弱电流）模式。 这种布置提供了具有较低时间平均功率消耗的较高速度运行。

公开(公告)号：US5394104A

公开(公告)日：1995-02-28

申请号：US293782

申请日：1994-08-22

申请人： Napoleon W. Lee

发明人： Napoleon W. Lee

IPC分类号： H03K3/3565 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  H03K17/22 ,  H03K3/3565

摘要： A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

摘要翻译： 提供上电复位电路，其将集成电路器件保持在复位模式，直到满足至少两个条件：电源电压Vcc必须高于指定值，并且器件中的读出放大器必须能够正常工作。 延迟电路和施密特触发电路还可以提高将器件从其复位模式释放的信号的稳定性。

公开(公告)号：US5991880A

公开(公告)日：1999-11-23

申请号：US190053

申请日：1998-11-10

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

摘要翻译： 用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。 在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。 如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。 在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。