公开(公告)号：US09503372B1

公开(公告)日：2016-11-22

申请号：US14634851

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L49/25 ,  H04L49/351

Abstract: An integrated circuit includes ingress ethernet ports and egress ethernet ports. A second ingress ethernet port is configurable to operate in a selected one of a command mode and a data mode. The ingress ethernet port does not power up in the command mode and can only be put into the command mode as a result of a port modeset command being received onto an ingress ethernet port operating in the command mode. A first ingress ethernet port powers up in the command mode. In the command mode the first ingress ethernet port can receive and carry out a port modeset command. Receiving and carrying out of the port modeset command causes one of the ingress ethernet ports identified by the port modeset command to operate in the command mode. A flow table structure adapted to store flow entries is used to determine which egress ethernet port outputs a packet.

Abstract translation: 集成电路包括入口以太网端口和出口以太网端口。 第二个入口以太网端口可配置为以选定的命令模式和数据模式之一运行。 入口以太网端口在命令模式下不上电，只能在端口模式命令接收到在命令模式下运行的入口以太网端口上进入命令模式。 第一个入口以太网端口在命令模式下上电。 在命令模式下，第一个入口以太网端口可以接收并执行端口模式命令。 接收和执行port modeset命令会导致port modeset命令标识的入口以太网端口之一在命令模式下运行。 使用适于存储流条目的流表结构来确定哪个出口以太网端口输出分组。

公开(公告)号：US09417656B2

公开(公告)日：2016-08-16

申请号：US14151688

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: H04L12/743 ,  G06F12/00 ,  H04L29/08 ,  G06F1/10 ,  G06F13/00 ,  G06F9/44

CPC classification number: G06F1/10 ,  G06F9/4498 ,  G06F12/00 ,  G06F13/00 ,  H04L45/7457 ,  H04L67/00

Abstract: An NFA (Non-deterministic Finite Automaton) circuit includes a hardware byte characterizer, a first matching circuit (performs a TCAM match function), a second matching circuit (performs a wide match function), a multiplexer that outputs a selected output from either the first or second matching circuits, and a storage device. N data values stored in first storage locations of the storage device are supplied to the first matching circuit as an N-bit mask value and are simultaneously supplied to the second matching circuit as N bits of an N+O-bit mask value. O data values stored in second storage locations of the storage device are supplied to the first matching circuit as the O-bit match value and are simultaneously supplied to the second matching circuit as O bits of the N+O-bit mask value. P data values stored in third storage locations are supplied onto the select inputs of the multiplexer.

Abstract translation: NFA（非确定性有限自动机）电路包括硬件字节表征器，第一匹配电路（执行TCAM匹配功能），第二匹配电路（执行宽匹配功能），多路复用器，其输出来自 第一或第二匹配电路和存储装置。 存储在存储装置的第一存储位置的N个数据值作为N位掩码值被提供给第一匹配电路，并且作为N + O位掩码值的N位被同时提供给第二匹配电路。 存储在存储装置的第二存储位置的O数据值被提供给第一匹配电路作为O比特匹配值，并且被同时提供给第二匹配电路作为N + O位掩码值的O比特。 存储在第三存储位置的P数据值被提供给多路复用器的选择输入。

公开(公告)号：US09413665B2

公开(公告)日：2016-08-09

申请号：US14464697

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F9/26 ,  H04L12/801 ,  G06F12/10 ,  H04L12/935 ,  H04L12/861 ,  G06F13/16

CPC classification number: H04L47/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F13/4234 ,  G06F2212/657 ,  H04L49/3072 ,  H04L49/9078

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. A device interacting with the packet engine can use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. Alternatively, the device can use a Linear Addressing Mode (LAM) to communicate with the packet engine. A PAM/LAM selection code field in a bus transaction value sent to the packet engine indicates whether PAM or LAM will be used.

Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 与分组引擎交互的设备可以使用PPI（分组部分标识符）寻址模式（PAM）与分组引擎进行通信，并指示分组引擎存储分组部分。 或者，设备可以使用线性寻址模式（LAM）与分组引擎进行通信。 发送到分组引擎的总线事务值中的PAM / LAM选择代码字段指示是否使用PAM或LAM。

公开(公告)号：US09342313B2

公开(公告)日：2016-05-17

申请号：US14037239

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  G06F9/38 ,  G06F9/30 ,  H04L12/741

CPC classification number: G06F9/3836 ,  G06F9/3004 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

公开(公告)号：US09298495B1

公开(公告)日：2016-03-29

申请号：US14724826

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F3/00 ,  G06F13/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F9/46 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F9/467 ,  G06F12/00 ,  G06F13/1615 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4234 ,  H04L45/745 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

公开(公告)号：US20160055112A1

公开(公告)日：2016-02-25

申请号：US14590920

申请日：2015-01-06

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

Abstract translation: 响应于从信用感知设备接收到一个新颖的“可返回PPI信用”命令，数据包引擎将为该设备维护的“信用回报”（CTBR）值发送回信用感知设备，并将零值 存储CTBR值。 信用感知设备将返回的信用额度添加到维护的“可用信用额”值。 信用感知设备使用“可用点数”值来确定是否可以发出PPI分配请求。 “可返回可用的PPI积分”命令不会导致任何PPI分配或解除分配。 在另一个新颖的方面，当信用感知设备的记录“可用可用”值为零或否定时，信用感知设备被允许向分组引擎发出一个PPI分配请求。 如果PPI分配请求不能被授权，则缓冲在分组引擎中，并在分组引擎内重新提交，直到分组引擎进行PPI分配。

公开(公告)号：US09262136B2

公开(公告)日：2016-02-16

申请号：US14074640

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/45 ,  G06F9/445

CPC classification number: G06F8/41 ,  G06F8/457 ,  G06F8/54

Abstract: A novel allocate instruction and a novel API call are received onto a compiler. The allocate instruction includes a symbol that identifies a non-memory resource instance. The API call is a call to perform an operation on a non-memory resource instance, where the particular instance is indicated by the symbol in the API call. The compiler replaces the API call with a set of API instructions. A linker then allocates a value to be associated with the symbol, where the allocated value is one of a plurality of values, and where each value corresponds to a respective one of the non-memory resource instances. After allocation, the linker generates an amount of executable code, where the API instructions in the code: 1) are for using the allocated value to generate an address of a register in the appropriate non-memory resource instance, and 2) are for accessing the register.

Abstract translation: 一个新的分配指令和一个新的API调用被接收到一个编译器上。 分配指令包括标识非内存资源实例的符号。 API调用是对非内存资源实例执行操作的调用，其中特定实例由API调用中的符号指示。 编译器使用一组API指令替换API调用。 链接器然后分配要与符号相关联的值，其中分配的值是多个值中的一个，并且其中每个值对应于非存储器资源实例中的相应一个。 分配后，链接器生成一定量的可执行代码，其中代码中的API指令：1）用于使用分配的值在适当的非内存资源实例中生成寄存器的地址，以及2）用于访问 登记册。

公开(公告)号：US20150370571A1

公开(公告)日：2015-12-24

申请号：US14311212

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30003 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3877 ,  G06F9/3881 ,  G06F15/825

Abstract: A pipelined run-to-completion processor has a special tripwire bus port and executes a novel tripwire instruction. Execution of the tripwire instruction causes the processor to output a tripwire value onto the port during a clock cycle when the tripwire instruction is being executed. A first multi-bit value of the tripwire value is data that is output from registers, and/or flags, and/or pointers, and/or data values stored in the pipeline. A field of the tripwire instruction specifies what particular stored values will be output as the first multi-bit value. A second multi-bit value of the tripwire value is a number that identifies the particular processor that output the tripwire value. The processor has a TE enable/disable control bit. This bit is programmable by a special instruction to disable all tripwire instructions. If disabled, a tripwire instruction is fetched and decoded but does not cause the output of a tripwire value.

Abstract translation: 流水线运行到完成处理器具有特殊的tripwire总线端口，并执行新颖的tripwire指令。 在执行tripwire指令时，执行tripwire指令会导致处理器在时钟周期内向端口输出绊线值。 tripwire值的第一多位值是从存储在流水线中的寄存器，/或标志，/或指针和/或数据值输出的数据。 tripwire指令的字段指定将作为第一个多位值输出什么特定的存储值。 tripwire值的第二个多位值是识别输出绊线值的特定处理器的数字。 处理器具有TE使能/禁止控制位。 该位可通过特殊指令进行编程，以禁用所有tripwire指令。 如果禁用，则取出并解码tripwire指令，但不会导致tripwire值的输出。

公开(公告)号：US09164730B2

公开(公告)日：2015-10-20

申请号：US14037303

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.

Abstract translation: 具有非确定性熵的比特流由自定时逻辑熵比特流生成器（STLEBSG）产生。 STLEBSG包括一个增量器和一个线性反馈移位寄存器（LFSR），两者均以自定时逻辑实现，作为异步状态机的一部分。 响应于命令，增量器异步地增加一次次数，然后停止，其中次数由命令确定。 对于增量器的每个增量，LFSR经历状态转换。 随着递增器递增，LFSR输出比特流。 如果命令是重复运行命令，则在增量程序停止后，增量程序将重新初始化，然后再次递增次数。 这种递增，停止，重新初始化和递增过程无限期地重复。 另一个命令导致加载器被加载。 另一个命令导致加载LFSR。

公开(公告)号：US20150293792A1

公开(公告)日：2015-10-15

申请号：US14251592

申请日：2014-04-12

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/4843 ,  G06F9/5027 ,  G06F9/5038 ,  G06F15/8007 ,  G06F15/8046 ,  G06F15/8053 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/22

Abstract: A general purpose PicoEngine Multi-Processor (PEMP) includes a hierarchically organized pool of small specialized picoengine processors and associated memories. A stream of data input values is received onto the PEMP. Each input data value is characterized, and from the characterization a task is determined. Picoengines are selected in a sequence. When the next picoengine in the sequence is available, it is then given the input data value along with an associated task assignment. The picoengine then performs the task. An output picoengine selector selects picoengines in the same sequence. If the next picoengine indicates that it has completed its assigned task, then the output value from the selected picoengine is output from the PEMP. By changing the sequence used, more or less of the processing power and memory resources of the pool is brought to bear on the incoming data stream. The PEMP automatically disables unused picoengines and memories.

Abstract translation: 通用PicoEngine多处理器（PEMP）包括一个分层组织的小型专用微型引擎处理器和相关存储器的池。 数据输入值流被接收到PEMP上。 每个输入数据值被表征，并且从表征确定任务。 Picoengines按顺序选择。 当序列中的下一个微型引擎可用时，然后给出输入数据值以及相关的任务分配。 picoengine然后执行任务。 输出微型引擎选择器以相同的顺序选择微型引线。 如果下一个微微引擎指示它已经完成其分配的任务，则从PEMP输出所选择的微微引擎的输出值。 通过改变所使用的顺序，或多或少地将该池的处理能力和存储器资源承担在输入数据流上。 PEMP自动禁用未使用的打印机和内存。