公开(公告)号：US20100202218A1

公开(公告)日：2010-08-12

申请号：US12367249

申请日：2009-02-06

申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C16/24

摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，其具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

公开(公告)号：US20100146189A1

公开(公告)日：2010-06-10

申请号：US12331206

申请日：2008-12-09

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C13/0069 ,  G11C2013/0088

摘要： Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value.

摘要翻译： 公开了非易失性存储器及其编程方法。 在一个实施例中，编程存储器阵列的方法包括接收一系列数据块，每个数据块具有要编程的位数，确定要在第一数据块中编程的位的数量，确定 要编程在第二数据块中的比特数，以及如果要在第一数据块中编程的比特数之和并且将第一和第二数据块并入到存储器阵列中， 第二数据块不大于最大值。

公开(公告)号：US08437175B2

公开(公告)日：2013-05-07

申请号：US13408389

申请日：2012-02-29

申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

IPC分类号： G11C11/24

CPC分类号： G11C16/12 ,  G11C16/24

摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，其具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

公开(公告)号：US08327062B2

公开(公告)日：2012-12-04

申请号：US12331206

申请日：2008-12-09

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G06F13/00 ,  G11C16/02 ,  G11C16/16

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C13/0069 ,  G11C2013/0088

摘要： Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first data block and the second data block into the memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. The first and second data blocks may or may not be adjacent data blocks. Improved programming efficiency may be achieved in a memory circuit when the maximum allowable current may be limited by the application or the size of a charge pump. Inverse data may be written in parallel if the sum is greater than the maximum value.

摘要翻译： 公开了非易失性存储器及其编程方法。 在一个实施例中，编程存储器阵列的方法包括接收一系列数据块，每个数据块具有要被编程的位数，确定要在第一数据块中编程的位的数量，确定 要在第二数据块中编程的比特数，以及如果要在第一数据块中编程的比特数的总和，并行地将第一数据块和第二数据块并入到存储器阵列中 并且第二数据块不大于最大值。 第一和第二数据块可以是或可以不是相邻的数据块。 当最大允许电流受应用或电荷泵的尺寸限制时，可在存储器电路中实现改进的编程效率。 如果和大于最大值，反数据可以并行写入。

公开(公告)号：US20100065891A1

公开(公告)日：2010-03-18

申请号：US12212097

申请日：2008-09-17

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： H01L23/52

CPC分类号： H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

摘要翻译： 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US20120155189A1

公开(公告)日：2012-06-21

申请号：US13408389

申请日：2012-02-29

申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/24

摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，该多路复用器具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

公开(公告)号：US20080056024A1

公开(公告)日：2008-03-06

申请号：US11846914

申请日：2007-08-29

申请人： Michael Bollu ,  Michael Sommer

发明人： Michael Bollu ,  Michael Sommer

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C16/26 ,  G11C2207/063

摘要： A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

摘要翻译： 用于读出存储在存储器中的存储器信息的装置具有积分器和比较器。 存储器在保持阶段提供泄漏电流，并且在读出阶段提供读出电流。 读出电流取决于存储的存储器信息。 积分器适于在保持阶段期间积分从泄漏电流导出的量，并提供与集成的泄漏电流相对应的泄漏电压。 积分器进一步适于在读出阶段期间积分从读出电流导出的量，并提供对应于积分读出电流的读出电压。 比较器可以将泄漏电压与读出电压进行比较，并根据比较提供对应于存储器信息的读出值。

公开(公告)号：US20050286296A1

公开(公告)日：2005-12-29

申请号：US11145541

申请日：2005-06-03

申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

公开(公告)号：US06563729B2

公开(公告)日：2003-05-13

申请号：US10127616

申请日：2002-04-22

申请人： Eric-Roger Brücklmeier ,  Michael Bollu ,  Tobias Schlager

发明人： Eric-Roger Brücklmeier ,  Michael Bollu ,  Tobias Schlager

IPC分类号： G11C1122

CPC分类号： G11C29/50016 ,  G11C11/22 ,  G11C29/50

摘要： A configuration is described for evaluating a signal that is read from a ferroelectric storage capacitor, in which, in addition to positive and negative polarization states, a weak polarization state is evaluated. Using the configuration, a data storage characteristic of the memory cells can be monitored, and a manipulation attempt can be detected.

公开(公告)号：US5751742A

公开(公告)日：1998-05-12

申请号：US626512

申请日：1996-04-02

申请人： Paul-Werner Von Basse ,  Michael Bollu ,  Roland Thewes ,  Doris Schmitt-Landsiedel

发明人： Paul-Werner Von Basse ,  Michael Bollu ,  Roland Thewes ,  Doris Schmitt-Landsiedel

IPC分类号： G11C8/04 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/86 ,  G06F11/1008 ,  G11C29/88

摘要： In a serially working memory unit with a memory matrix, a row selection unit and a column selection unit are configured such that, given faulty rows or columns, only correctable, single errors or errors of few successive bits occur. This memory unit offers advantages particularly for read-only memories since, due to the memory contents that are already determined during manufacture, substitute rows or columns can thereby not be provided.

摘要翻译： 在具有存储器矩阵的串行工作存储器单元中，行选择单元和列选择单元被配置为使得给定有故障的行或列仅发生少数连续位的可校正的单个错误或错误。 该存储单元特别对于只读存储器提供了优点，因为由于在制造期间已经确定的存储器内容，因此可以不提供代替行或列。