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32 条记录 (耗时 0.024 秒)

    Semiconductor memory having charge trapping memory cells and fabrication method
    1.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Semiconductor memory having charge trapping memory cells and fabrication method
    2.
    发明授权
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US07184291B2

    公开(公告)日：2007-02-27

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： G11C5/06

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    DEVICE AND METHOD FOR READING OUT MEMORY INFORMATION
    4.
    发明申请
    DEVICE AND METHOD FOR READING OUT MEMORY INFORMATION 有权
    用于读出存储器信息的装置和方法

    公开(公告)号：US20080056024A1

    公开(公告)日：2008-03-06

    申请号：US11846914

    申请日：2007-08-29

    申请人： Michael Bollu ,  Michael Sommer

    发明人： Michael Bollu ,  Michael Sommer

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C16/26 ,  G11C2207/063

    摘要： A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

    摘要翻译： 用于读出存储在存储器中的存储器信息的装置具有积分器和比较器。 存储器在保持阶段提供泄漏电流，并且在读出阶段提供读出电流。 读出电流取决于存储的存储器信息。 积分器适于在保持阶段期间积分从泄漏电流导出的量，并提供与集成的泄漏电流相对应的泄漏电压。 积分器进一步适于在读出阶段期间积分从读出电流导出的量，并提供对应于积分读出电流的读出电压。 比较器可以将泄漏电压与读出电压进行比较，并根据比较提供对应于存储器信息的读出值。

    System and method for level shifter
    7.
    发明授权
    System and method for level shifter 有权
    电平转换器的系统和方法

    公开(公告)号：US08130558B2

    公开(公告)日：2012-03-06

    申请号：US12367249

    申请日：2009-02-06

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

    IPC分类号： G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/24

    摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

    摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，其具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

    System and Method for Level Shifter
    8.
    发明申请
    System and Method for Level Shifter 有权
    液位移器系统与方法

    公开(公告)号：US20100202218A1

    公开(公告)日：2010-08-12

    申请号：US12367249

    申请日：2009-02-06

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

    IPC分类号： G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/24

    摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

    摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，其具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

    Programming Non Volatile Memories
    9.
    发明申请
    Programming Non Volatile Memories 有权
    编程非易失性存储器

    公开(公告)号：US20100146189A1

    公开(公告)日：2010-06-10

    申请号：US12331206

    申请日：2008-12-09

    申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

    发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C13/0069 ,  G11C2013/0088

    摘要： Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value.

    摘要翻译： 公开了非易失性存储器及其编程方法。 在一个实施例中，编程存储器阵列的方法包括接收一系列数据块，每个数据块具有要编程的位数，确定要在第一数据块中编程的位的数量，确定 要编程在第二数据块中的比特数，以及如果要在第一数据块中编程的比特数之和并且将第一和第二数据块并入到存储器阵列中， 第二数据块不大于最大值。

    DATA RETENTION MONITOR
    10.
    发明申请
    DATA RETENTION MONITOR 有权
    数据保持监控

    公开(公告)号：US20090034343A1

    公开(公告)日：2009-02-05

    申请号：US11831448

    申请日：2007-07-31

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016

    摘要： A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

    摘要翻译： 一种用于包括电压源和电压比较器的存储单元的数据保持监视器。 电压源适于向存储器单元提供可选择的电压。 可选择的电压包括读取电压和测试电压，测试电压大于读取电压。 电压比较器适于在将存储单元提供可选择的电压之后将存储单元的电压与参考电压进行比较。 当至少部分由测试电压产生的存储单元电压基本上等于参考电压时，存储单元保留数据。