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11.发明申请Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权具有II型全数字锁相环（PLL）的无线通信设备公开(公告)号：US20050212606A1
公开(公告)日：2005-09-29
申请号：US11122670
申请日：2005-05-04
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。
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公开(公告)号：US20050130618A1
公开(公告)日：2005-06-16
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。
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公开(公告)号：US20050025270A1
公开(公告)日：2005-02-03
申请号：US10924303
申请日：2004-08-23
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
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公开(公告)号：US09419635B2
公开(公告)日：2016-08-16
申请号：US14343932
申请日：2012-09-10
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
摘要翻译： 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器和配置用于参考光子入射到参考时钟的时间数字转换器系统，并且还包括参考时钟发生器，用于产生参考时钟 ，其中所述参考时钟发生器被配置为基于直到随后的光子入射的估计时间来调整所述参考时钟的频率。
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15.发明申请Single-Electron Injection/Extraction Device for a Resonant Tank Circuit and Method of Operation Thereof 有权用于谐振槽电路的单电子注入/提取装置及其操作方法公开(公告)号：US20080061892A1
公开(公告)日：2008-03-13
申请号：US11846987
申请日：2007-08-29
申请人： Robert Staszewski , Renaldi Winoto , Dirk Leipold
发明人： Robert Staszewski , Renaldi Winoto , Dirk Leipold
CPC分类号： H03B1/04 , H03B5/12 , H03B2202/027 , H03B2202/076
摘要： A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.
摘要翻译： 一种降低谐振回路中相位噪声的系统。 该系统包括被配置为将单个电子注入到振荡器电路槽电路中的单电子器件。 该系统还包括耦合到单电子器件并被配置为使得单电子器件基于谐振的极端（最大或最小）电特性输出的相位将单个电子注入到谐振回路中的同步器 坦克回路。
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16.发明申请METHOD OF DEFINING SEMICONDUCTOR FABRICATION PROCESS UTILIZING TRANSISTOR INVERTER DELAY PERIOD 有权定义半导体制造工艺的方法利用晶体管逆变器延迟时间公开(公告)号：US20070110194A1
公开(公告)日：2007-05-17
申请号：US11550878
申请日：2006-10-19
CPC分类号： H04L27/361 , H03L7/091 , H03L7/0991 , H03L7/1806
摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
摘要翻译： 一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。 逆时间的计算提供了每个模具中制造工艺变化的直接相关性。
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17.发明申请Apparatus and method for acquisition and tracking bank cooperation in a digitally controlled oscillator 有权用于在数控振荡器中采集和跟踪银行合作的装置和方法公开(公告)号：US20070085621A1
公开(公告)日：2007-04-19
申请号：US11551103
申请日：2006-10-19
申请人： Robert Staszewski , John Wallberg
发明人： Robert Staszewski , John Wallberg
IPC分类号： H03B5/12
CPC分类号： H03C3/095 , H03C3/0975 , H03L7/08 , H03L2207/50
摘要： A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.
摘要翻译： 一种用于在全数字锁相环（ADPLL）内的数字控制振荡器（DCO）中采集和跟踪存储体协作的新型装置和方法。 采集库的采集位用作调制范围的扩展。 PLL和TX调谐数据被分解（即分配）到采集组件和跟踪组件中。 这允许如现有技术方案那样使用两个不同的电容器组（即，跟踪和采集组）用于调制，而不仅仅是单个电容器组。 结合跟踪和采集位变容二极管，本发明的协作方案允许跟踪组重新对中以处理DCO的固有频率漂移和调制范围的扩大。
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18.发明申请Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术公开(公告)号：US20050104654A1
公开(公告)日：2005-05-19
申请号：US10712593
申请日：2003-11-13
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译： 改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。 该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。
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公开(公告)号：US20050025268A1
公开(公告)日：2005-02-03
申请号：US10924159
申请日：2004-08-23
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
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公开(公告)号：US07623838B2
公开(公告)日：2009-11-24
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。
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