公开(公告)号：US20070085623A1

公开(公告)日：2007-04-19

申请号：US11550957

申请日：2006-10-19

申请人： Robert Staszewski ,  John Wallberg

发明人： Robert Staszewski ,  John Wallberg

IPC分类号： H03L5/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L7/1806 ,  H03L2207/50 ,  H04L27/361 ,  H04L27/368

摘要： A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

摘要翻译： 一种用于在基于全数字锁相环（ADPLL）的数字控制振荡器（DCO）中增益归一化的新颖机制，其可操作地在调制路径和PLL环路之间分离增益归一化乘法功能。 调制环路（称为调制路径乘法器）的增益归一化包括全位分辨率高精度乘法函数。 另一方面，PLL环路的增益归一化具有显着更低的分辨率，因此需要较低复杂度的乘法器逻辑电路。

公开(公告)号：US20070085622A1

公开(公告)日：2007-04-19

申请号：US11551050

申请日：2006-10-19

申请人： John Wallberg ,  Robert Staszewski

发明人： John Wallberg ,  Robert Staszewski

IPC分类号： H03B5/12

CPC分类号： H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/1806

摘要： A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an α gear shift circuit, a p gear shift circuit and an optional IIR gear shift circuit. The α gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The α gear shift circuit comprises an accumulator whose output is multiplied by the gain value ρ. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables α and ρ which may be accomplished in software.

摘要翻译： 一种新颖的换档机构，可以以连续和可逆的方式调节锁相环（PLL）电路的环路增益。 可以增加环路增益以加宽环路的带宽，并且还可以减小环路带宽的窄度。 该机构包括一个阿尔法换档电路，一个p换档电路和一个可选的IIR换档电路。 阿尔法换档电路包括无限脉冲响应（IIR）滤波，其能够在发生变速事件时实现PLL回路的无中断运行。 阿尔法换档电路包括一个累加器，其输出乘以增益值rho。 本发明通过配置可以在软件中实现的环路增益变量α和rho来实现正或负方向上的多个换档。

公开(公告)号：US20070085579A1

公开(公告)日：2007-04-19

申请号：US11551150

申请日：2006-10-19

申请人： John Wallberg ,  Robert Staszewski

发明人： John Wallberg ,  Robert Staszewski

IPC分类号： H03L7/06 ,  H03D3/24

CPC分类号： H03L7/08 ,  H03L2207/50

摘要： A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

摘要翻译： 一种新颖的机理，用于使用频率检测器观察和比较参考和可变PLL环路信号的微分相位。 然后累积产生的相位微分误差以产生相位误差。 与频率检测器的环路的操作在数学上等同于相位检测器。 频率误差累加器用于产生频率误差的积分。 频率误差累加器还能够在检测到足够大的扰动时停止频率的累积，从而有效地冻结环路的操作，因为随后的频率误差更新不被累积。 在去除相位冻结事件时，恢复频率误差的累积，从而恢复正常循环操作。

公开(公告)号：US20070182496A1

公开(公告)日：2007-08-09

申请号：US11551124

申请日：2006-10-19

申请人： John Wallberg ,  Robert Staszewski ,  Vanessa Bodrero

发明人： John Wallberg ,  Robert Staszewski ,  Vanessa Bodrero

IPC分类号： H03B5/12

CPC分类号： G01R31/31727 ,  H03B2201/0283 ,  H03J2200/10

摘要： A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested

摘要翻译： 一种新颖的测试机制，用于测试诸如数字控制晶体振荡器（DCXO）中使用的大电容阵列。 本发明适用于在其阵列解码电路中采用动态元件匹配的DCXO电路中。 本发明结合了DCXO正常运行期间DEM的使用与大大减少所需测试次数的测试技术。 本发明逐行测试阵列中的电容器，其中一行中的所有电容器被集中测试并被处理为单个实体，这导致测试时间显着减少。 这允许由于与被测试的整个电容器相关联的较大电容而测量显着更高的频率偏差

公开(公告)号：US20060103566A1

公开(公告)日：2006-05-18

申请号：US11274965

申请日：2005-11-15

申请人： Sudheer Vemulapalli ,  John Wallberg ,  Prasant Vallur ,  Robert Staszewski

发明人： Sudheer Vemulapalli ,  John Wallberg ,  Prasant Vallur ,  Robert Staszewski

IPC分类号： H03M1/12

CPC分类号： H04L27/361 ,  G04F10/005 ,  H03L7/091

摘要： A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

摘要翻译： 一种新颖的时间数字转换器（TDC），用作数字无线电处理器内的全数字PLL中的相位/频率检测器和电荷泵替换。 TDC内核基于伪差分数字架构，使其对NMOS和PMOS晶体管不匹配不敏感。 时间转换分辨率等于CMOS的逆变器传播延迟，例如20 ps，这是CMOS中最优的逻辑电平再生定时。 TDC自校准，估计精度优于1％。 TDC电路还可以用作大型SoC模具中模拟电路的CMOS工艺强度估计器。 该电路还采用电源管理电路，将功耗降至非常低的水平。

公开(公告)号：US20070085621A1

公开(公告)日：2007-04-19

申请号：US11551103

申请日：2006-10-19

申请人： Robert Staszewski ,  John Wallberg

发明人： Robert Staszewski ,  John Wallberg

IPC分类号： H03B5/12

CPC分类号： H03C3/095 ,  H03C3/0975 ,  H03L7/08 ,  H03L2207/50

摘要： A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.

摘要翻译： 一种用于在全数字锁相环（ADPLL）内的数字控制振荡器（DCO）中采集和跟踪存储体协作的新型装置和方法。 采集库的采集位用作调制范围的扩展。 PLL和TX调谐数据被分解（即分配）到采集组件和跟踪组件中。 这允许如现有技术方案那样使用两个不同的电容器组（即，跟踪和采集组）用于调制，而不仅仅是单个电容器组。 结合跟踪和采集位变容二极管，本发明的协作方案允许跟踪组重新对中以处理DCO的固有频率漂移和调制范围的扩大。

公开(公告)号：US20060132431A1

公开(公告)日：2006-06-22

申请号：US11015562

申请日：2004-12-17

申请人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

发明人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

IPC分类号： G09G5/00

CPC分类号： G06F3/0317 ,  G06F1/1616 ,  G06F1/1626 ,  G06F1/1684 ,  G06F1/1686 ,  G06F1/169 ,  G06F1/1694 ,  G06F1/1698 ,  G06F3/0354 ,  G06F3/03547 ,  G06F3/04886 ,  H04M2250/52 ,  H04W52/0267 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/23

摘要： System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.

摘要翻译： 使用多功能设备与数字计算机进行接口的系统和方法。 优选实施例包括多功能设备，其包括被配置为处理信息并调节多功能设备的操作的控制器，耦合到控制器的传感器，被配置为捕获多功能设备的移动中的信息或 应用于多功能装置的物体的移动以及将信息提供给控制器，其中所述信息用于确定移动信息。 多功能设备还包括还耦合到控制器的射频电路，射频电路被配置为经由多个通信网络与其他设备交换信息，其中其他设备之一是计算机，并且共享的信息是 来自多功能设备的运动信息。

公开(公告)号：US07801262B2

公开(公告)日：2010-09-21

申请号：US11551150

申请日：2006-10-19

申请人： John Wallberg ,  Robert B. Staszewski

发明人： John Wallberg ,  Robert B. Staszewski

IPC分类号： H03D3/24

CPC分类号： H03L7/08 ,  H03L2207/50

摘要： A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

摘要翻译： 一种新颖的机理，用于使用频率检测器观察和比较参考和可变PLL环路信号的微分相位。 然后累积产生的相位微分误差以产生相位误差。 与频率检测器的环路的操作在数学上等同于相位检测器。 使用频率误差累加器来产生频率误差的积分。 频率误差累加器还能够在检测到足够大的扰动时停止频率的累积，从而有效地冻结环路的操作，因为随后的频率误差更新不被累积。 在去除相位冻结事件时，恢复频率误差的累积，从而恢复正常循环操作。

公开(公告)号：US07746185B2

公开(公告)日：2010-06-29

申请号：US11551103

申请日：2006-10-19

申请人： Robert B. Staszewski ,  John Wallberg

发明人： Robert B. Staszewski ,  John Wallberg

IPC分类号： H03B5/08 ,  H03C3/22 ,  H03L7/085

CPC分类号： H03C3/095 ,  H03C3/0975 ,  H03L7/08 ,  H03L2207/50

摘要： A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.

摘要翻译： 一种用于在全数字锁相环（ADPLL）内的数字控制振荡器（DCO）中采集和跟踪存储库协作的新型装置和方法。 采集库的采集位用作调制范围的扩展。 PLL和TX调谐数据被分解（即分配）到采集组件和跟踪组件中。 这允许如现有技术方案那样使用两个不同的电容器组（即，跟踪和采集组）用于调制，而不仅仅是单个电容器组。 结合跟踪和采集位变容二极管，本发明的协作方案允许跟踪组重新对中以处理DCO的固有频率漂移和调制范围的扩大。

公开(公告)号：US07205924B2

公开(公告)日：2007-04-17

申请号：US11274965

申请日：2005-11-15

申请人： Sudheer K. Vemulapalli ,  John Wallberg ,  Prasant K. Vallur ,  Robert B. Staszewski

发明人： Sudheer K. Vemulapalli ,  John Wallberg ,  Prasant K. Vallur ,  Robert B. Staszewski

IPC分类号： H03M1/50

CPC分类号： H04L27/361 ,  G04F10/005 ,  H03L7/091

摘要： A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

摘要翻译： 一种新颖的时间数字转换器（TDC），用作数字无线电处理器内的全数字PLL中的相位/频率检测器和电荷泵替换。 TDC内核基于伪差分数字架构，使其对NMOS和PMOS晶体管不匹配不敏感。 时间转换分辨率等于CMOS的逆变器传播延迟，例如20 ps，这是CMOS中最优的逻辑电平再生定时。 TDC自校准，估计精度优于1％。 TDC电路还可以用作大型SoC模具中模拟电路的CMOS工艺强度估计器。 该电路还采用电源管理电路，将功耗降至非常低的水平。