公开(公告)号：US20100070958A1

公开(公告)日：2010-03-18

申请号：US12449160

申请日：2007-11-15

申请人： Masamichi Takagi

发明人： Masamichi Takagi

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： Provided is a program parallelizing method and a program parallelizing apparatus that enable to efficiently generate a parallelized program with shorter parallel execution time.An instruction is scheduled by referring to inter-instruction dependency. A dependency between an instruction in a function fp/f0 and an instruction of a function fq of its descendant is analyzed, and parallelization is performed with the analysis result. First, an instruction of a deeper function fq is relatively scheduled to analyze whether each instruction has dependency with an instruction of another function fp. When there is inter-instruction dependency, scheduling of the instruction of the function fq is performed so as to maintain the dependency and realize the shortest execution time.

摘要翻译： 提供了一种能够以较短的并行执行时间有效地生成并行化程序的程序并行化方法和程序并行化装置。 通过参考指令间相关性来安排指令。 分析函数fp / f0中的指令与其后代的函数fq的指令之间的依赖关系，并进行分析结果的并行处理。 首先，相对地调度更深层函数fq的指令来分析每个指令是否与另一函数fp的指令相关。 当存在指令间相关性时，执行函数fq的指令的调度以保持依赖性并实现最短的执行时间。

公开(公告)号：US08531963B2

公开(公告)日：2013-09-10

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04J3/14

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US08214521B2

公开(公告)日：2012-07-03

申请号：US12629048

申请日：2009-12-02

申请人： Masamichi Takagi ,  Yoshiki Seo ,  Akio Yamada ,  Takeo Hosomi

发明人： Masamichi Takagi ,  Yoshiki Seo ,  Akio Yamada ,  Takeo Hosomi

IPC分类号： G06F15/16 ,  G06F9/46

CPC分类号： G06F9/5038

摘要： Systems and methods are disclosed to process streaming data units (tuples) for an application using a plurality of processing units, the application have a predetermined processing time requirement, by changing an operator-set applied to the tuple by a processing unit, on a tuple-by-tuple basis; estimating code requirement for potential operators based on processing unit capability; and assigning the potential operators to the processing units.

摘要翻译： 公开了系统和方法来处理使用多个处理单元的应用的流数据单元（元组），该应用具有预定的处理时间要求，通过在元组上改变由处理单元应用于元组的操作符集 元组 基于处理单元能力估算潜在运营商的代码要求; 并将潜在的操作者分配给处理单元。

公开(公告)号：US08108719B2

公开(公告)日：2012-01-31

申请号：US12441289

申请日：2007-09-13

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F11/00

CPC分类号： G06F11/2043 ,  G06F11/2023 ,  G06F11/2025 ,  G06F11/203 ,  G06F11/2033 ,  G06F11/2035

摘要： An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

摘要翻译： 信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。 信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。 故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元，使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作，切换OS和执行环境， 在故障处理单元上操作，使得它们在替代处理单元上操作，并且切换由故障处理单元使用的共享资源，使得它可用于替代处理单元。

公开(公告)号：US20100077259A1

公开(公告)日：2010-03-25

申请号：US12447524

申请日：2007-10-17

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F9/30 ,  G06F11/07

CPC分类号： G06F11/277

摘要： An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

摘要翻译： 公开了一种用于执行半导体集成电路的屏蔽测试的装置，所述半导体集成电路包括多个处理器，每个处理器具有用于指令执行信息的输出信号，并且所述处理器可编程地可操作。 用于执行半导体集成电路的屏蔽测试的装置包括：指令/数据信号同步电路，用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路，用于比较从各个处理器输出的指令执行信息，以确定所述处理器中的任何一个是否输出了不同的指令执行信息。

公开(公告)号：US20100070802A1

公开(公告)日：2010-03-18

申请号：US12529458

申请日：2008-02-19

申请人： Hiroaki Inoue ,  Masamichi Takagi

发明人： Hiroaki Inoue ,  Masamichi Takagi

IPC分类号： G06F11/273

CPC分类号： G01R31/31724 ,  G01R31/31723 ,  G01R31/318536 ,  G06F11/2236

摘要： A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).

摘要翻译： 半导体集成电路包括与互连网络（1000）连接的多个核（99）和与所述互连网络（1000）连接的测试控制器（500），并且发出与 通过互连网络（1000）对核心（99）进行测试。 互连网络（1000）由分别用作多个核（99）和测试控制器（500）的连接接口的多个适配器（3000）和多个路由器（2000）组成，多个路由器 连接多个适配器（3000）。 与核心（99）连接的适配器（3000）包括核心测试单元，用于根据从测试控制器（500）经由互连网络（1000）接收的测试控制请求代替连接到其自身的核心（99） 。

公开(公告)号：US07429469B2

公开(公告)日：2008-09-30

申请号：US10491498

申请日：2002-10-09

申请人： Satoru Yokomizo ,  Takeshi Fukuchi ,  Fumio Osakada ,  Keiji Matsumoto ,  Masamichi Takagi ,  Akinori Ohta

发明人： Satoru Yokomizo ,  Takeshi Fukuchi ,  Fumio Osakada ,  Keiji Matsumoto ,  Masamichi Takagi ,  Akinori Ohta

IPC分类号： C07H21/04 ,  C12P7/62 ,  C12N15/74 ,  C12N1/21

CPC分类号： C07K14/40 ,  C07K2319/01 ,  C12N9/88 ,  C12N15/52 ,  C12P7/625

摘要： This invention relates to a method of producing polyesters resulting from homopolymerization or copolymerization of a 3-hydroxyalkanoic acid(s) and having biodegradability and good physical properties using yeasts as hosts. By constructing at least one enzyme gene involved in polyester synthesis by adding a DNA coding a peroxisome-targeting signal, introducing an enzyme gene expression cassette containing that gene into yeast, and cultivating the thus-obtained transformant, it becomes possible to cause accumulation of a polyester resulting from homopolymerization or copolymerization of a 3-hydroxyalkanoic acid(s) in yeast cells and recover the polyester from the culture.

摘要翻译： 本发明涉及由使用酵母作为宿主的3-羟基烷酸的均聚或共聚而具有生物降解性和良好物理性能的聚酯的制造方法。 通过添加编码过氧化物酶体靶向信号的DNA构建至少一个参与聚酯合成的酶基因，将含有该基因的酶基因表达盒导入酵母中，培养由此得到的转化体，可以使 由酵母细胞中的3-羟基链烷酸的均聚或共聚得到的聚酯，并从培养物中回收聚酯。

公开(公告)号：US20080044878A1

公开(公告)日：2008-02-21

申请号：US10505229

申请日：2003-04-08

申请人： Tetsuya Nagaoka ,  Satoru Yokomizo ,  Kenji Miyamoto ,  Fumio Osakada ,  Keiji Matsumoto ,  Masamichi Takagi ,  Akinori Ota

发明人： Tetsuya Nagaoka ,  Satoru Yokomizo ,  Kenji Miyamoto ,  Fumio Osakada ,  Keiji Matsumoto ,  Masamichi Takagi ,  Akinori Ota

IPC分类号： C07H21/04 ,  C12N1/00 ,  C12P1/02

CPC分类号： C07K14/4716 ,  C12N9/1025 ,  C12N15/815

摘要： The present invention provides a production method of a copolymeric polyester which comprises culturing an ACT1 gene promoter shown under SEQ ID NO: 9, a GAP3 gene promoter shown under SEQ ID NO: 10; a PMA1 gene promoter shown under SEQ ID NO: 11, and, a TEF1 gene promoter shown under SEQ ID NO: 12; a plasmid which contains the gene expression unit comprising said promoter; a transformed cell as resulting from transformation of the said plasmid; and said transformed cell.

摘要翻译： 本发明提供共聚聚酯的制造方法，其包括培养SEQ ID NO：9所示的ACT1基因启动子，SEQ ID NO：10所示的GAP3基因启动子; SEQ ID NO：11所示的PMA1基因启动子和SEQ ID NO：12所示的TEF1基因启动子; 含有包含所述启动子的基因表达单元的质粒; 由所述质粒转化产生的转化细胞; 和转化细胞。

公开(公告)号：US4879230A

公开(公告)日：1989-11-07

申请号：US813193

申请日：1985-12-24

申请人： Masamichi Takagi ,  Keiji Yano ,  Ichiro Shibuya ,  Minoru Morikawa

发明人： Masamichi Takagi ,  Keiji Yano ,  Ichiro Shibuya ,  Minoru Morikawa

IPC分类号： C12N15/81

CPC分类号： C12N15/81

摘要： The present invention relates to plasmids whose hosts can be Escherichia coli and some kinds of yeasts, namely, shuttle vectors, as well as to processes for producing said plasmids. There are provided in the present invention (1) plasmids containing an autonomously replicating sequence of Candida maltosa, Leu 2 gene derived from Saccharomyces cerevisiae and an ampicillin resistance gene and (2) plasmids further containing a tetracycline resistance gene as well as the genes described in (1).The plasmids (shuttle vectors) of the present invention can be utilized as follows. A useful foreign gene is inserted into plasmids of the present invention; using the resulting new plasid, Escherichia coli is transformed and cultured in order to obtain the plasmid in a large amount; and using this plasmid, Saccharomyces cerevisiae or Candida maltosa as a host is allowed to produce useful substances such as hormones and enzymes on a large scale.

摘要翻译： 本发明涉及其宿主可以是大肠杆菌和一些种类的酵母的质粒，即穿梭载体，以及生产所述质粒的方法。 在本发明中提供了（1）含有自愿复制的假丝酵母（Candida maltosa）的质粒，来源于酿酒酵母的Leu 2基因和氨苄青霉素抗性基因的质粒和（2）进一步含有四环素抗性基因的质粒以及描述于 （1）。 本发明的质粒（穿梭载体）可以如下使用。 将有用的外源基因插入本发明的质粒中; 使用所得的新的质粒，转化和培养大肠杆菌以获得大量的质粒; 使用该质粒，可以将酿酒酵母或麦芽假丝酵母作为宿主大量产生有用的物质如激素和酶。

公开(公告)号：US08638665B2

公开(公告)日：2014-01-28

申请号：US12935035

申请日：2009-04-30

申请人： Masamichi Takagi ,  Sunao Torii

发明人： Masamichi Takagi ,  Sunao Torii

IPC分类号： G06F11/00

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251

摘要： A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

摘要翻译： 路由器包括：飞行到达时间管理部，其记录作为第一次接收分组的时间的飞行到达时间，从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道，并且需要用于输出通道的横截面部分，在该输出通道之前，应该在该飞行器到达时间之前输出该分组; 开关分配单元，对所述输出通道请求进行仲裁，并进行输入/输出连接关系设定处理; 以及开关分配验证部，其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。