公开(公告)号：US10256967B2

公开(公告)日：2019-04-09

申请号：US15863983

申请日：2018-01-08

Applicant: Novatek Microelectronics Corp.

Inventor： Chang-Cheng Huang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/093 ,  H03L7/089

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

公开(公告)号：US10147717B2

公开(公告)日：2018-12-04

申请号：US15247943

申请日：2016-08-26

Applicant: Novatek Microelectronics Corp.

Inventor： Federico Agustin Altolaguirre ,  Ming-Dou Ker ,  Tzu-Chien Tzeng ,  Ju-Lin Huang

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06

Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

公开(公告)号：US09780085B1

公开(公告)日：2017-10-03

申请号：US15373491

申请日：2016-12-09

Applicant: Novatek Microelectronics Corp.

Inventor： Rong-Kun Chang ,  Jie-Ting Chen ,  Chun-Yu Lin ,  Ming-Dou Ker ,  Tzu-Chien Tzeng ,  Ping-Chang Lin

IPC: H01L27/02 ,  H01L49/02

CPC classification number: H01L27/0292 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0288 ,  H01L28/10 ,  H02H9/046

Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

公开(公告)号：US20170069618A1

公开(公告)日：2017-03-09

申请号：US15247943

申请日：2016-08-26

Applicant: Novatek Microelectronics Corp.

Inventor： Federico Agustin Altolaguirre ,  Ming-Dou Ker ,  Tzu-Chien Tzeng ,  Ju-Lin Huang

IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H01L27/0292 ,  H01L27/0635 ,  H02H9/046

Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

Abstract translation: 在本公开中，静电放电（ESD）保护电路耦合在第一电源轨和第二电源轨之间以排放任何ESD应力。 ESD保护电路包括检测电路，触发电路和双可控硅整流器（DSCR）装置。 当ESD应力施加到第一或第二电力轨时，检测电路可以首先检测ESD应力并将检测信号输出到触发电路。 触发电路基于检测信号和ESD应力的极性产生触发信号。 然后，基于在同一类型的至少两个晶体管之间的公共节点处接收的触发信号来对称地触发DSCR设备。 示例性ESD保护电路可以在纳米级制造的集成电路中实现，并且在保持低待机漏电流和相对较小的硅封装的同时实现良好的ESD鲁棒性。

公开(公告)号：US09008253B2

公开(公告)日：2015-04-14

申请号：US13775119

申请日：2013-02-23

Applicant: NOVATEK Microelectronics Corp.

Inventor： Tzu-Chien Tzeng ,  Hung-Yi Cheng

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/08 ,  H03L7/10 ,  H03L7/107

CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03L7/103 ,  H03L7/1072 ,  H04L7/033

Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Abstract translation: 一种在支持多个频带的时钟数据恢复装置中使用的控制方法，用于控制时钟数据恢复装置从多个频带中选择工作频带并产生用于产生重新定时数据的恢复时钟，包括： 具有数据频率的串行数据流; 使多个频带的每个频带对应于多个频带组，其中每个频带组包括至少一个频带并对应于不同的频率范围; 根据数据频率和锁定电压范围，从多个频带组中选择频带组作为粗调谐频带组; 以及根据数据频率，锁定电压范围和用于产生恢复时钟的粗调谐频带组从多个频带中选择频带。

公开(公告)号：US10725486B2

公开(公告)日：2020-07-28

申请号：US16052654

申请日：2018-08-02

Applicant: Novatek Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: G05F1/46 ,  H03K5/24 ,  G01R19/165

Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

公开(公告)号：US20190130824A1

公开(公告)日：2019-05-02

申请号：US16000891

申请日：2018-06-06

Applicant: Novatek Microelectronics Corp.

Inventor： Tzu-Chien Tzeng ,  Po-Hsiang Fang

IPC: G09G3/3225

Abstract: The disclosure provides a sensing apparatus and an operation method thereof. The sensing apparatus includes a sensing circuit, an analog-to-digital converter (ADC) circuit, a disturbing circuit and an output circuit. The sensing circuit is configured to output a sensing signal indicating a sensing result of a sensing line of the display panel. The ADC circuit is coupled to the sensing circuit to receive the sensing signal and outputs sensing data related to the sensing signal. The disturbing circuit is coupled to the ADC circuit to receive the sensing data and generates a time-variant disturbance component to disturb the sensing data to generate disturbed data. The output circuit is coupled to the disturbing circuit to receive the disturbed data.

公开(公告)号：US10121777B2

公开(公告)日：2018-11-06

申请号：US15275492

申请日：2016-09-26

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Yu Lin ,  Jie-Ting Chen ,  Ming-Dou Ker ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Ju-Lin Huang

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

公开(公告)号：US20140112425A1

公开(公告)日：2014-04-24

申请号：US13775119

申请日：2013-02-23

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Tzu-Chien Tzeng ,  Hung-Yi Cheng

IPC: H04L7/033

CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03L7/103 ,  H03L7/1072 ,  H04L7/033

Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Abstract translation: 一种在支持多个频带的时钟数据恢复装置中使用的控制方法，用于控制时钟数据恢复装置从多个频带中选择工作频带并产生用于产生重新定时数据的恢复时钟，包括： 具有数据频率的串行数据流; 使多个频带的每个频带对应于多个频带组，其中每个频带组包括至少一个频带并对应于不同的频率范围; 根据数据频率和锁定电压范围，从多个频带组中选择频带组作为粗调谐频带组; 以及根据数据频率，锁定电压范围和用于产生恢复时钟的粗调谐频带组从多个频带中选择频带。