公开(公告)号：US10432882B2

公开(公告)日：2019-10-01

申请号：US15876494

申请日：2018-01-22

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/374 ,  H04N5/378 ,  A61B1/05 ,  H04N5/225 ,  A61B1/045 ,  H04N5/361 ,  A61B1/07 ,  G02B23/24 ,  A61B1/06

Abstract: An imaging device includes a plurality of pixels, a reference current generation circuit, a differential current generation circuit, a reference voltage generation circuit, a conversion circuit, and an output circuit. The differential current generation circuit generates a differential current according to a difference between a pixel current and a reference current. The conversion circuit converts the differential current into an output voltage on the basis of a first reference voltage. A second reference voltage is higher than the tint reference voltage when the output voltage at the time of resetting of the pixels is higher than the output voltage at the time of exposure of the pixels. The second reference voltage is lower than the first reference voltage when the output voltage at the time of resetting of the pixels is lower than the output voltage at the time of exposure of the pixels.

公开(公告)号：US20180199802A1

公开(公告)日：2018-07-19

申请号：US15921937

申请日：2018-03-15

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: A61B1/05 ,  A61B1/00

CPC classification number: A61B1/051 ,  A61B1/00018 ,  A61B1/00096 ,  A61B1/045 ,  A61B1/05 ,  G02B23/243 ,  H04N5/235 ,  H04N5/378 ,  H04N2005/2255

Abstract: An endoscope system includes an imaging element, a voltage-current conversion circuit, a first coaxial cable, and an impedance conversion circuit. The imaging element generates a first voltage. The voltage-current conversion circuit is disposed inside or outside the imaging element and converts the first voltage into a first current. The first coaxial cable has a first conductor and a second conductor. The second conductor is disposed outside the first conductor. The first current is transmitted through the first conductor. The first current transmitted through the first conductor is input to the impedance conversion circuit. The impedance conversion circuit outputs a second current according to the first current. A second voltage according to the first current is input to the second conductor.

公开(公告)号：US20170302873A1

公开(公告)日：2017-10-19

申请号：US15635516

申请日：2017-06-28

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/378 ,  H04N5/376 ,  H03K5/00 ,  H03K5/13 ,  H03K5/06 ,  H01L27/146

CPC classification number: H04N5/378 ,  H01L27/14636 ,  H01L27/14643 ,  H03K5/06 ,  H03K5/133 ,  H03K2005/00078 ,  H03K2005/00234 ,  H04N5/3765

Abstract: An imaging device includes an imaging unit, a reference signal generation unit, m (m is an integer of 3 or more) number of column delay units, and a plurality of column AD conversion units. The plurality of column delay units is arranged so as to correspond to two or more and less than m of the column AD conversion units. Each of the plurality of column delay units includes a first delay circuit. The first delay circuit generates a plurality of first delay clocks. The column AD conversion unit includes a comparison unit, a latch unit, and a counter unit. The comparison unit compares a pixel signal with a reference signal, and outputs a control signal corresponding to a comparison result. The latch unit includes a plurality of latch circuits that latches the plurality of first delay clocks on the basis of a state change of the control signal.

公开(公告)号：US20170187978A1

公开(公告)日：2017-06-29

申请号：US15455270

申请日：2017-03-10

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/376 ,  H04N5/3745 ,  H03M7/30 ,  H03K5/15 ,  H03M1/20

CPC classification number: H04N5/3765 ,  H03K5/15066 ,  H03M1/123 ,  H03M1/20 ,  H03M1/502 ,  H03M1/56 ,  H03M7/30 ,  H04N5/3745 ,  H04N5/378

Abstract: An encoding circuit includes a clock generating unit having a delay circuit in which n (n is a power of 2) delay units are connected together a latch unit configured to latch the plurality of delayed signals; and an encoding unit configured to encode state of each of the plurality of delayed signals, wherein the encoding unit encodes the state of each of the plurality of delayed signals by performing: a first operation of determining a position at which logic states of two or more delayed signals in a signal group change from High to Low, a second operation of determining a position at which logic states of two or more delayed signals in the signal group change from Low to High, and a third operation of determining that logic states of two or more signals including at least one delayed signal in the signal group are predetermined states.

公开(公告)号：US09294114B2

公开(公告)日：2016-03-22

申请号：US14090569

申请日：2013-11-26

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H03K3/01 ,  G01J1/44 ,  H03M1/34 ,  H04N5/376 ,  H04N5/378 ,  H03M1/56 ,  H03K5/00

CPC classification number: H03M1/34 ,  H03K2005/00241 ,  H03M1/56 ,  H04N5/3765 ,  H04N5/378

Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.

Abstract translation: 提供了参考信号发生电路，AD转换电路和成像装置。 时钟发生单元包括延迟部分，其包括延迟单元，每个延迟单元延迟输入信号并输出​​延迟信号，并且基于从延迟部分输出的信号输出低阶相位信号。 高阶电流源单元单元包括高阶电流源单元，每个单元产生相同的恒定电流。 低阶电流源单元单元包括加权的低阶电流源单元，以产生恒定电流，该恒定电流的电流值与由高阶电流源单元产生的恒定电流的当前值的预定比例相差。 基于通过基于低阶相位信号划分时钟而获得的时钟来执行高阶电流源单元的选择。

公开(公告)号：US20150341583A1

公开(公告)日：2015-11-26

申请号：US14817821

申请日：2015-08-04

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/3745 ,  H04N5/376 ,  H04N5/363 ,  H04N5/378 ,  H04N5/63

CPC classification number: H04N5/3745 ,  H03M1/08 ,  H03M1/123 ,  H03M1/56 ,  H04N5/363 ,  H04N5/37455 ,  H04N5/3765 ,  H04N5/378 ,  H04N5/63

Abstract: An imaging device includes: an imaging section in which a plurality of unit pixels having a photoelectric conversion element are arranged in the form of a matrix; a reference signal generating section configured to generate a reference signal that increases or decreases with a passage of time; a comparison section that includes a differential amplifier including a first input terminal electrically connected to the reference signal generating section and a second input terminal electrically connected to the unit pixels and configured to compare voltages of the first input terminal and the second input terminal and is arranged for each column or for a plurality of columns of a pixel array of the imaging section; and a measurement section configured to measure a comparison time from when the comparison section starts comparison until the comparison ends and generate data corresponding to the comparison time.

Abstract translation: 一种成像装置，包括：成像部，其中具有光电转换元件的多个单位像素以矩阵的形式排列; 参考信号产生部分，被配置为产生随着时间的推移而增加或减小的参考信号; 比较部分，其包括差分放大器，包括电连接到参考信号产生部分的第一输入端子和电连接到单位像素的第二输入端子，并且被配置为比较第一输入端子和第二输入端子的电压， 对于每个列或者用于成像部分的像素阵列的多个列; 以及测量部，被配置为测量从比较部开始比较直到比较结束的比较时间，并生成与比较时间对应的数据。

公开(公告)号：US20140098271A1

公开(公告)日：2014-04-10

申请号：US14037842

申请日：2013-09-26

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/3745 ,  H03M1/34

CPC classification number: H04N5/37455 ,  G04F10/005 ,  H03M1/08 ,  H03M1/123 ,  H03M1/34 ,  H03M1/56

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract translation: AD转换电路可以包括：参考信号生成单元，其产生随着时间的推移而增加或减小的参考信号; 比较单元，包括将要进行AD转换的模拟信号与参考信号进行比较的第一比较电路和第二比较电路; 时钟生成单元，其包括延迟电路，其中多个延迟单元彼此连接，并且基于从所述多个延迟单元中的每一个输出的时钟信号输出第一下相位信号和第二下相位信号; 锁存单元，包括锁存第一下相位信号的逻辑状态的第一锁存电路和锁存第二下相位信号的逻辑状态的第二锁存电路; 以及计数单元，基于从时钟生成单元输出的第二下相位信号进行计数。

公开(公告)号：US20140036120A1

公开(公告)日：2014-02-06

申请号：US13957116

申请日：2013-08-01

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/374

CPC classification number: H04N5/374 ,  H04N5/378

Abstract: An image pickup device may include: an image capturing unit; a reference signal generation unit; a row selection unit that selects and controls each unit pixel for every row of the array of the unit pixels; a comparison unit including a differential amplifier unit and a reset unit; a measurement unit that measures a comparison time from a comparison start to a comparison end; and a change unit that includes a switch element and a second capacitive element in which one end of the second capacitive element is connected to the first input terminal and the other end of the second capacitive element is connected to a first voltage source via the switch element at a time of a reset operation by the reset unit and connected to a second voltage source different from the first voltage source via the switch element after the reset operation.

Abstract translation: 图像拾取装置可以包括：图像捕获单元; 参考信号生成单元; 行选择单元，其选择并控制单位像素的阵列的每行的每个单位像素; 比较单元，包括差分放大器单元和复位单元; 测量单元，其测量从比较开始到比较结束的比较时间; 以及包括开关元件和第二电容元件的改变单元，其中第二电容元件的一端连接到第一输入端子，而第二电容元件的另一端经由开关元件连接到第一电压源 在复位单元进行复位操作时，在复位操作之后经由开关元件连接到与第一电压源不同的第二电压源。

公开(公告)号：US20130327925A1

公开(公告)日：2013-12-12

申请号：US13909203

申请日：2013-06-04

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/335

CPC classification number: H04N5/3355 ,  H04N5/3575 ,  H04N5/378

Abstract: An image pickup device may include: an image capturing unit; a reference signal generation unit; a comparison unit that compares analog signals to the reference signal and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signals; a clock generation unit; a latch unit that retains the low-order phase signal as a latch signal at a timing related to the end of the comparison process; a count unit that counts a signal related to one of the low-order phase signals and generates a high-order digital signal; a detection unit that generates a low-order digital signal by sequentially comparing logic states of a plurality of bits of the latch signal retained by the corresponding latch unit and encoding the latch signal; and an arithmetic unit that performs an arithmetic process.

Abstract translation: 图像拾取装置可以包括：图像捕获单元; 参考信号生成单元; 比较单元，其将模拟信号与参考信号进行比较，并在参考信号相对于模拟信号满足预定条件的定时结束比较处理; 时钟发生单元; 锁存单元，在与比较处理结束相关的定时保持低位相位信号作为锁存信号; 计数单元，对与低阶相位信号之一相关的信号进行计数，并生成高阶数字信号; 检测单元，其通过顺序地比较由对应的锁存单元保持的锁存信号的多个位的逻辑状态并对锁存信号进行编码来生成低阶数字信号; 以及执行算术处理的算术单元。

公开(公告)号：US20130146751A1

公开(公告)日：2013-06-13

申请号：US13759383

申请日：2013-02-05

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H03K21/00 ,  H01L27/146 ,  H03M1/34

CPC classification number: H03K21/00 ,  G04F10/005 ,  H01L27/14601 ,  H03M1/34 ,  H03M1/56 ,  H04N5/3742 ,  H04N5/378

Abstract: A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.

Abstract translation: 时间检测电路可以包括：延迟单元，被配置为具有多个延迟单元，每个延迟单元延迟并输出输入信号，并且在与第一脉冲的输入有关的第一定时开始操作; 锁存单元，被配置为锁存所述多个延迟单元的逻辑状态; 计数单元，被配置为基于从所述多个延迟单元中的一个延迟单元输出的时钟来执行计数操作; 计数锁存单元，被配置为锁存所述计数单元的状态; 以及闩锁控制单元，被配置为在与第二脉冲的输入相关的第二定时使能所述锁存单元，并且使所述锁存单元和所述计数锁存单元在从所述锁存单元和所述计数锁存单元经过预定时间的第三定时执行锁存器 第二时间。