公开(公告)号：US20160131711A1

公开(公告)日：2016-05-12

申请号：US14535647

申请日：2014-11-07

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/31713 ,  G01R31/31727 ,  G01R31/318544

Abstract: Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.

Abstract translation: 本公开的实现涉及用于在数字集成电路的结构测试期间混合高速和低速时钟信号以提高测试精度和效率的装置和/或方法。 具体地，该装置和/或方法允许测试装置通过释放低速时钟信号的一个或多个时钟周期来执行电路的卡位测试。 此外，不必重置电路的测试，电路的高速测试可以由测试装置进行。 在一个实施例中，通过激活与电路设计相关联的模式信号来进行速度测试，所述模式信号指示从内部时钟信号到被释放的电路的一个或多个时钟周期。 测试设备可以以低速时钟信号返回卡位测试，或使用高速内部时钟信号继续进行高速测试。

公开(公告)号：US12277041B2

公开(公告)日：2025-04-15

申请号：US18332453

申请日：2023-06-09

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F11/20 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US10467139B2

公开(公告)日：2019-11-05

申请号：US15859037

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Damien Walker ,  Priyambada Mitra ,  Ali Vahidsafa ,  Matthew Cohen ,  Josephus Ebergen ,  Andrew Brock

IPC: G06F12/0817 ,  G06F12/0813 ,  G06F12/0842

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

公开(公告)号：US10452547B2

公开(公告)日：2019-10-22

申请号：US15858787

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Damien Walker ,  Priyambada Mitra ,  Ali Vahidsafa ,  Matthew Cohen ,  Josephus Ebergen ,  Andrew Brock

IPC: G06F12/00 ,  G06F12/0817 ,  G06F12/128 ,  G06F12/0813

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

公开(公告)号：US10248520B2

公开(公告)日：2019-04-02

申请号：US15202308

申请日：2016-07-05

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F11/00 ,  G06F11/25

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting an at-speed functional test on a silicon wafer of an integrated circuit. In one embodiment, the method includes utilizing a first clock signal during a first portion of the test and a second clock signal during a second portion. The clock signals are configured such that a first subset of the logic stages of the circuit are tested at-speed by the first portion and a second subset of the logic stages of the circuit are tested at-speed. Further, in one embodiment, the first subset and the second subset comprise all of the logic stages of the circuit design. Through the configuration of the clock signals, the tester may ensure that each stage of the circuit design is tested at-speed such that a more accurate at-speed test result may be obtained in a low current environment.

公开(公告)号：US10007629B2

公开(公告)日：2018-06-26

申请号：US14598640

申请日：2015-01-16

Applicant: Oracle International Corporation

Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

IPC: G06F11/00 ,  G06F13/40 ,  G06F11/30 ,  G06F11/22

CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

公开(公告)号：US09710273B2

公开(公告)日：2017-07-18

申请号：US14549742

申请日：2014-11-21

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30145 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/2028 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US09632141B2

公开(公告)日：2017-04-25

申请号：US14316468

申请日：2014-06-26

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Roger Charles Mistely

IPC: G01R31/3185 ,  G01R31/319 ,  G06F11/22

CPC classification number: G01R31/31922 ,  G01R31/318552 ,  G01R31/318563 ,  G01R31/318594 ,  G01R31/31908 ,  G06F11/2236 ,  G06F11/263

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.

公开(公告)号：US20160357571A1

公开(公告)日：2016-12-08

申请号：US14731216

申请日：2015-06-04

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F9/44 ,  G06F13/362

CPC classification number: G06F9/4401 ,  G06F13/362

Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

Abstract translation: 本公开的实现涉及通过将复位控制器连接到复位控制器总线或其他类型的通用总线来实现微处理器或其他类型的计算系统的复位控制器的系统和/或方法。 通过复位总线，用于产生系统的复位序列的复位控制器信号可以通过总线传送到系统的组件，而不是利用组件和复位控制器之间的直接线连接。 构成复位总线的导线然后可以运行到在复位序列期间重新启动的微处理器设计的一个或多个组件。 这些部件中的每一个还可以包括复位控制器电路，其被设计为从复位控制器接收复位控制信号并对信号进行解码以确定接收到的信号是否适用于该部件。

公开(公告)号：US09460013B2

公开(公告)日：2016-10-04

申请号：US14479191

申请日：2014-09-05

Applicant: Oracle International Corporation

Inventor： David Richard Smentek ,  Ali Vahidsafa ,  Venkatram Krishnaswamy ,  Thirumalai Swamy Suresh

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F2212/62 ,  G06F2212/621

Abstract: A method for removal of an offlining cache agent, including: initiating an offlining of the offlining cache agent from communicating with a plurality of participating cache agents while a first transaction is in progress; setting, based on initiating the offlining, an ignore response indicator corresponding to the offlining cache agent on each of the plurality of participating cache agents; offlining, based on setting the ignore response indicator, the offlining cache agent; and ignoring, based on setting the ignore response indicator, a first response to the transaction from the offlining cache agent.

Abstract translation: 一种用于去除最终缓存代理的方法，包括：在第一次交易进行期间，发起关闭高速缓存代理与多个参与高速缓存代理的通信; 基于发起所述离线，设置与所述多个参与高速缓存代理中的每一个上的所述高速缓存代理相对应的忽略响应指示符; 根据设置忽略响应指示符，即关闭缓存代理; 并且基于设置忽略响应指示符忽略来自所述高速缓存代理的对所述事务的第一响应。