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    Integrated circuit current metering using voltage variation detection circuit
    11.
    发明授权
    Integrated circuit current metering using voltage variation detection circuit 有权

    公开(公告)号：US10296063B2

    公开(公告)日：2019-05-21

    申请号：US15474635

    申请日：2017-03-30

    Applicant: Oracle International Corporation

    Inventor： Yifan YangGong ,  Sebastian Turullols ,  Vijay Srinivasan

    IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

    Abstract: An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

    INTEGRATED CIRCUIT CURRENT METERING USING VOLTAGE VARIATION DETECTION CIRCUIT
    12.
    发明申请
    INTEGRATED CIRCUIT CURRENT METERING USING VOLTAGE VARIATION DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20180284867A1

    公开(公告)日：2018-10-04

    申请号：US15474635

    申请日：2017-03-30

    Applicant: Oracle International Corporation

    Inventor： Yifan YangGong ,  Sebastian Turullols ,  Vijay Srinivasan

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296

    Abstract: An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

    Micro-benchmark analysis optimization for microprocessor designs
    16.
    发明授权
    Micro-benchmark analysis optimization for microprocessor designs 有权
    微处理器设计的微基准分析优化

    公开(公告)号：US09483603B2

    公开(公告)日：2016-11-01

    申请号：US14293763

    申请日：2014-06-02

    Applicant: Oracle International Corporation

    Inventor： Haowei Zhang ,  Xiaoying Shen ,  Sebastian Turullols

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/11 ,  G06F17/16 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84 ,  G06F2217/86

    Abstract: Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

    Abstract translation: 实施例包括用于优化微处理器设计的微基准分析的系统和方法。 例如，实施例寻求生成一组微基准和相关联的加权因子，其可以用于以对于细粒度（例如，RTL）模拟）有效地定义加权聚合工作负载条件，其方式是足够的代理 预测商业工作量情况。 微型基准测试套件可以比商业工作量更高效地模拟，因此使用微型基准套件作为商业工作负载的代理可以提供许多好处，包括更有效的迭代设计。

    HIGH SENSITIVITY DIGITAL VOLTAGE DROOP MONITOR FOR INTEGRATED CIRCUITS
    17.
    发明申请
    HIGH SENSITIVITY DIGITAL VOLTAGE DROOP MONITOR FOR INTEGRATED CIRCUITS 有权
    用于集成电路的高灵敏度数字电压监视器

    公开(公告)号：US20160033576A1

    公开(公告)日：2016-02-04

    申请号：US14691332

    申请日：2015-04-20

    Applicant: Oracle International Corporation

    Inventor： Sebastian Turullols ,  Vijay Srinivasan ,  Changku Hwang

    IPC: G01R31/317 ,  G01R19/25

    CPC classification number: G01R31/31725 ,  G01R31/3004 ,  G01R31/31937 ,  G06F1/3206 ,  G06F1/3296 ,  H03K3/037 ,  H03K5/133 ,  H03K5/159

    Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.

    Abstract translation: 本公开的实现涉及用于通过数字采样电路测量集成电路的片上电压电平的系统和/或方法。 特别地，系统和/或方法利用基于延迟线的模数 - 数字采样电路，其产生随时间的电压读数，例如在每个高频时钟周期。 在一个实施例中，数字采样电路或数字电压监视电路包括粗略延迟分量或电路，其进一步延迟时钟信号通过延迟线的传播。 粗延迟电路可以被编程为延迟信号通过延迟线的传播，以便允许时钟或测试信号的多个边沿同时沿着延迟线行进并且增加电路的灵敏度。 也可以通过选择构成电路的部件的类型和配置有恒定电源电压的时钟抖动监视电路来获得数字电压监视器电路的附加灵敏度。

    Load line compensation in power monitoring
    18.
    发明授权
    Load line compensation in power monitoring 有权

    公开(公告)号：US11086377B2

    公开(公告)日：2021-08-10

    申请号：US15965963

    申请日：2018-04-29

    Applicant: Oracle International Corporation

    Inventor： Lin Zhang ,  Yifan YangGong ,  Sebastian Turullols

    IPC: G06F1/28 ,  G06F1/08

    Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

    Statistical temperature sensor calibration apparatus and methodology
    19.
    发明授权
    Statistical temperature sensor calibration apparatus and methodology 有权

    公开(公告)号：US10768057B2

    公开(公告)日：2020-09-08

    申请号：US15695883

    申请日：2017-09-05

    Applicant: Oracle International Corporation

    Inventor： Sebastian Turullols ,  Ha Pham ,  Changku Hwang ,  Yifan YangGong ,  Qing Xie

    IPC: G01K7/00 ,  G01K1/00 ,  G01K15/00 ,  G01K7/01

    Abstract: A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

    Micro-benchmark analysis optimization for microprocessor designs
    20.
    发明授权
    Micro-benchmark analysis optimization for microprocessor designs 有权

    公开(公告)号：US10102323B2

    公开(公告)日：2018-10-16

    申请号：US15291459

    申请日：2016-10-12

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Haowei Zhang ,  Xiaoying Shen ,  Sebastian Turullols

    IPC: G06F17/50 ,  G06F17/11 ,  G06F17/16

    Abstract: Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

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