公开(公告)号：US06930554B2

公开(公告)日：2005-08-16

申请号：US10623047

申请日：2003-07-18

申请人： Jyoti Mondal ,  Neil L. Calanca ,  Matthew R. Miller

发明人： Jyoti Mondal ,  Neil L. Calanca ,  Matthew R. Miller

IPC分类号： H03F1/22 ,  H03F3/45 ,  H03G3/30 ,  H03G3/10

CPC分类号： H03F1/223 ,  H03F1/22 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/411 ,  H03F2203/45481 ,  H03G3/3052 ,  H03G3/3057

摘要： A variable gain control amplifier (10) and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier (10) includes an amplifier stage including at least a first intermediate fixed gain stage (22) operative to produce a first intermediate signal (30) in response to the input signal (20). The variable gain control amplifier (10) further includes at least a second intermediate fixed gain stage (24) operative to produce an output signal (18) in response to the first intermediate signal (30). A feedback circuit (16) is operative to produce a gain control signal (32) in response to the output signal (18). A gain control circuit (26) is coupled to the at least first intermediate fixed gain stage (22) and the second intermediate fixed gain stage (24), and receives the gain control signal (32) to control an amplitude of the intermediate signal (30).

摘要翻译： 可变增益控制放大器（10）和方法提供基本恒定的输入阻抗和输出阻抗，并且提供基本上恒定的噪声系数和三阶谐波。 可变增益控制放大器（10）包括放大器级，至少包括第一中间固定增益级（22），用于响应输入信号（20）产生第一中间信号（30）。 可变增益控制放大器（10）还包括至少第二中间固定增益级（24），其响应于第一中间信号（30）而产生输出信号（18）。 反馈电路（16）用于响应于输出信号（18）产生增益控制信号（32）。 增益控制电路（26）耦合到至少第一中间固定增益级（22）和第二中间固定增益级（24），并且接收增益控制信号（32）以控制中间信号 30）。

公开(公告)号：US06750704B1

公开(公告)日：2004-06-15

申请号：US10340335

申请日：2003-01-09

申请人： Lawrence Edwin Connell ,  Craig S. Petrie ,  Matthew R. Miller

发明人： Lawrence Edwin Connell ,  Craig S. Petrie ,  Matthew R. Miller

IPC分类号： H03F102

CPC分类号： H03F3/45753 ,  H03F2200/331

摘要： A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.

摘要翻译： 差分放大器包括具有第一和第二输入装置的差分输入级，并具有第一和第二输入电极以及第一和第二输出端子。 差分负载级包括分别具有第一和第二控制电极的第一和第二负载装置。 负载级耦合到差分输入级以及第一和第二输出端。 第一和第二分离电容偏置网络耦合到第一和第二输出端子，并分别耦合到第一和第二控制电极。 在偏移消除阶段期间，输入电极耦合到公共电压。 在放大阶段期间，差分输入信号被施加到输入电极。

公开(公告)号：US5521941A

公开(公告)日：1996-05-28

申请号：US620601

申请日：1990-11-29

申请人： David G. Wiatrowski ,  Matthew R. Miller ,  Christopher N. Kurby

发明人： David G. Wiatrowski ,  Matthew R. Miller ,  Christopher N. Kurby

IPC分类号： H04L25/06

CPC分类号： H04L25/062 ,  H04L25/066 ,  Y10T307/664

摘要： Symbol recovery for multi-level digital signals has traditionally been difficult because of the nature of the eye pattern output by the discriminator (103), and especially its response to a noisy or impeded signal environment. This method and apparatus for recovery thresholds adjusts (411 and 417) to the current state of the discriminator (103) output of the received signal, based on an attenuated (301) version of that signal. Using a fast adjust mode and slow adjust mode, the threshold generating circuitry (331 and 361) adapts to the signal based on data from the received signal fed into lock detectors (329 and 359) which determine the mode to use.

摘要翻译： 传统上由于鉴别器（103）输出的眼图的性质，特别是其对噪声或阻碍的信号环境的响应，多级数字信号的符号恢复是困难的。 该恢复阈值的方法和装置基于该信号的衰减（301）版本，调整（411和417）到接收信号的鉴别器（103）输出的当前状态。 使用快速调整模式和慢速调整模式，阈值产生电路（331和361）根据来自确定使用模式的锁定检测器（329和359）的接收信号的数据适应信号。

公开(公告)号：US20120265947A1

公开(公告)日：2012-10-18

申请号：US13086936

申请日：2011-04-14

申请人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

发明人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

IPC分类号： G06F12/00

CPC分类号： G06F3/0631 ,  G06F3/0671 ,  G06F9/5016 ,  G06F12/0223

摘要： In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

摘要翻译： 响应于从应用线程接收到的存储器分配请求，获得随机数（例如，从先前填充有多个随机数的随机数列表）。 基于随机数来确定与包括存储器的多个块的区域相关联的位图的至少一部分中的起始位置。 从起始位置开始扫描位图的一部分，以识别与多个块的可用块对应的位图中的位置，并将该可用块的指示返回给应用程序线程。

公开(公告)号：US5182761A

公开(公告)日：1993-01-26

申请号：US649083

申请日：1991-01-31

申请人： Donald R. Beyer ,  Matthew R. Miller ,  Krsman Martinovich

发明人： Donald R. Beyer ,  Matthew R. Miller ,  Krsman Martinovich

IPC分类号： H03D3/02 ,  H03L7/107 ,  H04L7/033 ,  H04L7/08 ,  H04L7/10

CPC分类号： H04L7/0331 ,  H04L7/08 ,  H04L7/10

摘要： A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.

摘要翻译： 公开了一种数据传输系统接收机，其接收格式化的数据流（302）并且以至少第一带宽模式和第二带宽模式之一进行操作。 格式化数据流（302）包括多个数据边缘（108,110），并由第一时钟信号（320）进行采样。 使用定义从一个逻辑状态到另一逻辑状态的转换的多个时钟边缘（102,104）来定义“早期”和“晚期”数据边缘出现。 这些事件被累积在累加器（310,312）中，并用作产生相位调整时钟信号（320）的时钟计数器（318）的输入。 另外，数据传输接收机包括检测器（330），用于检测有限数据流（306）何时与相位调整时钟信号（320）同步，并且根据预定算法，能够切换相位调制信号 锁定电路从第一带宽模式到第二带宽模式。

公开(公告)号：US08671261B2

公开(公告)日：2014-03-11

申请号：US13086936

申请日：2011-04-14

申请人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

发明人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F3/0631 ,  G06F3/0671 ,  G06F9/5016 ,  G06F12/0223

摘要： In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

摘要翻译： 响应于从应用线程接收到的存储器分配请求，获得随机数（例如，从先前填充有多个随机数的随机数列表）。 基于随机数来确定与包括存储器的多个块的区域相关联的位图的至少一部分中的起始位置。 从起始位置开始扫描位图的一部分，以识别与多个块的可用块对应的位图中的位置，并将该可用块的指示返回给应用程序线程。

公开(公告)号：US20100019944A1

公开(公告)日：2010-01-28

申请号：US12445029

申请日：2006-10-13

申请人： Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

发明人： Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

IPC分类号： H03M1/12 ,  H03M3/00

CPC分类号： H03M3/392 ,  H03M3/40

摘要： An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

摘要翻译： 模数转换器装置包括耦合到第二积分器的第一积分器。 第一和第二积分器耦合以提供复极。 第一积分器选择性地与第二积分器电可去耦，从而去除复极。

公开(公告)号：US07609779B2

公开(公告)日：2009-10-27

申请号：US11363463

申请日：2006-02-27

申请人： Poojan A. Wagh ,  Lawrence E. Connell ,  Matthew R. Miller

发明人： Poojan A. Wagh ,  Lawrence E. Connell ,  Matthew R. Miller

IPC分类号： H04L27/00

CPC分类号： H04L27/2071

摘要： An RF modulator supporting wide-band signals includes IQ modulation by interleaving the in-phase and quadrature signals. The modulator can be implemented using an integrated circuit having a baseband in-phase stage that receives an in-phase analog input signal, a baseband quadrature stage that receives a quadrature analog input signal, and a switching mixer having a plurality of switches. The switching mixer receives in-phase and quadrature signals from the baseband in-phase stage and the baseband quadrature stage. The switching mixer produces a differential signal combining the in-phase and quadrature signals by interleaving the signals over a plurality of phases of a carrier period.

摘要翻译： 支持宽带信号的RF调制器通过交织同相和正交信号来包括IQ调制。 可以使用具有接收同相模拟输入信号的基带同相级的集成电路，接收正交模拟输入信号的基带正交级和具有多个开关的开关混频器来实现调制器。 开关混频器从基带同相级和基带正交级接收同相和正交信号。 开关混频器通过在载波周期的多个相位上交织信号来产生组合同相和正交信号的差分信号。

公开(公告)号：US06697001B1

公开(公告)日：2004-02-24

申请号：US10324684

申请日：2002-12-19

申请人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

发明人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

IPC分类号： H03M302

CPC分类号： H03M3/356 ,  H03M3/43 ,  H03M3/456

摘要： Systems and methods are described for a continuous-time sigma-delta modulator with discrete time common-mode feedback. The method includes calculating an integrator input signal as a difference between an input signal and a modulation feedback signal, continuous time integrating the integrator input signal to produce an integrator output signal having a common mode voltage, determining the common mode voltage of the integrator output signal using a discrete-time process, determining an integrator feedback signal as a function of the common-mode voltage and feeding back the feedback signal to the integrator in order to maintain the common mode voltage at a substantially constant value, sampling and quantizing the integrator output signal to produce a sigma-delta modulated output signal and converting the sigma-delta modulated output signal from a digital signal to an analog signal, to produce the modulation feedback signal.

摘要翻译： 对具有离散时间共模反馈的连续时间Σ-Δ调制器描述了系统和方法。 该方法包括：计算积分器输入信号作为输入信号和调制反馈信号之间的差值，连续时间积分积分器输入信号以产生具有共模电压的积分器输出信号，确定积分器输出信号的共模电压 使用离散时间过程，确定作为共模电压的函数的积分器反馈信号并将反馈信号反馈到积分器，以便将共模电压保持在基本恒定的值，对积分器输出进行采样和量化 信号以产生Σ-Δ调制输出信号，并将Σ-Δ调制输出信号从数字信号转换成模拟信号，以产生调制反馈信号。

公开(公告)号：US06693572B1

公开(公告)日：2004-02-17

申请号：US10358055

申请日：2003-02-04

申请人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

发明人： Omid Oliaei ,  Matthew R. Miller ,  Patrick L. Rakers

IPC分类号： H03M300

CPC分类号： H03M3/382 ,  H03M3/43 ,  H03M3/456

摘要： Systems and methods are described for a digital tuning scheme for continuous-time sigma-delta modulation. The method includes integrating a voltage from a voltage source using a discrete-time integrator to produce a discrete-time integrator output, continuous-time integrating a current from a controllable current source to produce a continuous-time integrator output, quantizing the difference between the continuous-time integrator output and the discrete-time integrator output to produce a quantizer output, controlling a polarity of the controllable current source with the quantizer output, counting the quantizer output to produce a feedback signal, and tuning the controllable current source as a function of the feedback signal.

摘要翻译： 描述了用于连续时间Σ-Δ调制的数字调谐方案的系统和方法。 该方法包括使用离散时间积分器积分来自电压源的电压以产生离散时间积分器输出，将来自可控电流源的电流连续时间积分以产生连续时间积分器输出，量化 连续时间积分器输出和离散时间积分器输出以产生量化器输出，通过量化器输出来控制可控电流源的极性，对量化器输出进行计数以产生反馈信号，以及调节可控电流源作为一个功能 的反馈信号。