公开(公告)号：US08316366B2

公开(公告)日：2012-11-20

申请号：US12061554

申请日：2008-04-02

申请人： Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

发明人： Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/46

CPC分类号： G06F9/466 ,  G06F9/3842 ,  G06F9/3851 ,  G06F12/0842

摘要： Embodiments of the present invention provide a system that executes a transaction on a simultaneous speculative threading (SST) processor. In these embodiments, the processor includes a primary strand and a subordinate strand. Upon encountering a transaction with the primary strand while executing instructions non-transactionally, the processor checkpoints the primary strand and executes the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand. When the subordinate strand non-transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate the first strand ID. When the primary strand transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate a second strand ID.

摘要翻译： 本发明的实施例提供了一种在同时推测的线程（SST）处理器上执行交易的系统。 在这些实施例中，处理器包括主链和从属链。 在非事务性地执行指令时遇到与主链的事务时，处理器检查主链，并且与主链执行事务，同时继续非随意地执行与下级链的延迟指令。 当下级链在事务期间非事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第一个链ID。 当主链在事务期间事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第二个链ID。

公开(公告)号：US08065485B2

公开(公告)日：2011-11-22

申请号：US12470639

申请日：2009-05-22

申请人： Gideon N. Levinsky ,  Paul Caprioli ,  Sherman H. Yip

发明人： Gideon N. Levinsky ,  Paul Caprioli ,  Sherman H. Yip

IPC分类号： G06F12/00 ,  G06F9/26

CPC分类号： G06F12/0864 ,  G06F12/1027 ,  G06F2212/271

摘要： A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

摘要翻译： 公开了一种用于以快速方式或缓存方式存储二进制信息的方法。 该方法包括接收要存储在具有多个方式的高速缓冲存储器中的二进制信息块。 多种方式包括方法的第一子集和方法的第二子集，其中来自第一方法子集之一的第一执行核心的高速缓存访​​问具有比来自第二子集的第二子集 方法。 该方法还包括基于预定访问等待时间和与二进制信息块相关联的一个或多个参数确定是否将二进制信息块存储为第一组方式之一或第二组路径之一。

公开(公告)号：US07650487B2

公开(公告)日：2010-01-19

申请号：US11371143

申请日：2006-03-08

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip

IPC分类号： G06F9/44

CPC分类号： G06F9/30087 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/3017 ,  G06F9/3838 ,  G06F9/3857

摘要： A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.

摘要翻译： 用于协调处理器中允许指令执行无序的指令的执行的技术包括解码根据处理器的指令集定义的特定指令。 然后将对应于特定指令的辅助指令序列引入到可执行操作流中。 相应的助手序列包括第一人造依赖指令，其对与实际不用作特定指令执行的操作的寄存器源或目标的寄存器进行编码依赖关系。

公开(公告)号：US20090265532A1

公开(公告)日：2009-10-22

申请号：US12104159

申请日：2008-04-16

申请人： Paul Caprioli ,  Sherman H. Yip ,  Gideon Levinsky

发明人： Paul Caprioli ,  Sherman H. Yip ,  Gideon Levinsky

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F12/0862

摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.

摘要翻译： 本发明的实施例执行反预取指令。 这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。 在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。 这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

公开(公告)号：US20090182956A1

公开(公告)日：2009-07-16

申请号：US12014217

申请日：2008-01-15

申请人： Paul Caprioli ,  Martin Karlsson ,  Sherman H. Yip

发明人： Paul Caprioli ,  Martin Karlsson ,  Sherman H. Yip

IPC分类号： G06F9/46 ,  G06F12/08

CPC分类号： G06F12/084 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/126 ,  G06F2212/1016

摘要： Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.

摘要翻译： 本发明的实施例提供一种在支持事务存储器的处理器上执行事务的系统。 系统通过在处理器上执行事务来启动。 在执行事务期间，系统将存储放在存储缓冲区中。 此外，当事务期间第一个存储被放置在存储缓冲区中时，系统设置stores_en遇到的指示符。 完成交易后，系统确定是否设置了stores_en遭遇指示符。 如果是这样，系统就会发出一个缓存，将事务期间放置在存储缓冲区中的存储提交到高速缓存，然后在存储已提交后，在事务之后恢复执行程序代码。 否则，系统将在事务之后恢复执行程序代码，而不发出缓存信号。

公开(公告)号：US20080172549A1

公开(公告)日：2008-07-17

申请号：US11654271

申请日：2007-01-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F11/3612

摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.

摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。

公开(公告)号：US07257700B2

公开(公告)日：2007-08-14

申请号：US11053382

申请日：2005-02-07

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip ,  Marc Tremblay

IPC分类号： G06F9/48

CPC分类号： G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.

摘要翻译： 本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。 该系统在具有按顺序架构的处理器内操作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。 在操作期间，在正常执行模式下执行程序期间，系统以程序顺序发出执行指令。 在发生指令（发射点指令）期间遇到使处理器进入推测执行模式的条件（发射条件）时，系统产生检查点，该检查点随后可用于将程序的执行返回到 启动点指令，并以推测执行模式开始执行。 当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点从启动点指令以正常执行模式恢复执行。 在这样做时，系统确保在进入投机执行模式之前处于短延迟记分板中的条目，以及尚未解决的条目，以便在从启动时恢复执行时防止寄存器RAW危险， 点指令。

公开(公告)号：US08572356B2

公开(公告)日：2013-10-29

申请号：US12652641

申请日：2010-01-05

申请人： Sherman H. Yip ,  Paul Caprioli

发明人： Sherman H. Yip ,  Paul Caprioli

IPC分类号： G06F9/00

CPC分类号： G06F9/3842 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3895

摘要： Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.

摘要翻译： 公开了技术和结构，用于支持检查点的处理器以有效的侦察模式进行操作，同时最大数量的支持的检查点是活动的。 在侦察模式下的操作可以包括使用旁路逻辑和一组寄存器存储位置来存储和/或转发在侦察模式期间计算的飞行中指令结果。 这些转发结果可以在侦察模式期间用于计算其他飞行中指令的存储器加载地址，并且处理器可以相应地使数据从这些计算的存储器加载地址中预取。 该组寄存器存储位置可以包括工作寄存器文件或多端口寄存器文件的活动部分。

公开(公告)号：US08181002B1

公开(公告)日：2012-05-15

申请号：US11655655

申请日：2007-01-18

申请人： Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

发明人： Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F7/00

CPC分类号： G06F9/383 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint during the speculative-execution episode. Next, the system merges the first checkpoint with the second checkpoint during the speculative-execution episode, wherein merging the first and second checkpoints conserves processor resources.

摘要翻译： 本发明的一个实施例提供了一种将处理器上的检查点合并的系统。 系统通过在推测性执行情节期间推测地执行指令来开始。 然后系统在推测执行情节期间生成第一个检查点和第二个检查点。 接下来，在推测执行情节期间，系统将第一检查点与第二检查点合并，其中合并第一和第二检查点节省处理器资源。

公开(公告)号：US08041900B2

公开(公告)日：2011-10-18

申请号：US12014217

申请日：2008-01-15

申请人： Paul Caprioli ,  Martin Karlsson ,  Sherman H. Yip

发明人： Paul Caprioli ,  Martin Karlsson ,  Sherman H. Yip

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/126 ,  G06F2212/1016

摘要： Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.

摘要翻译： 本发明的实施例提供一种在支持事务存储器的处理器上执行事务的系统。 系统通过在处理器上执行事务来启动。 在执行事务期间，系统将存储放在存储缓冲区中。 此外，当事务期间第一个存储被放置在存储缓冲区中时，系统设置stores_en遇到的指示符。 完成交易后，系统确定是否设置了stores_en遭遇指示符。 如果是这样，系统就会发出一个缓存，将事务期间放置在存储缓冲区中的存储提交到高速缓存，然后在存储已提交后，在事务之后恢复执行程序代码。 否则，系统将在事务之后恢复执行程序代码，而不发出缓存信号。