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31 条记录 (耗时 0.03 秒)

    CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
    11.
    发明授权
    CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
    具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法

    公开(公告)号：US06828630B2

    公开(公告)日：2004-12-07

    申请号：US10338103

    申请日：2003-01-07

    申请人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

    发明人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

    IPC分类号： H01L2976

    CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

    摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

    摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

    Comprehensive process for low temperature epitaxial growth
    13.
    发明授权
    Comprehensive process for low temperature epitaxial growth 失效
    低温外延生长的综合工艺

    公开(公告)号：US5378651A

    公开(公告)日：1995-01-03

    申请号：US56697

    申请日：1993-04-30

    申请人： Paul D. Agnello ,  Detlev A. Gruetzmacher ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

    发明人： Paul D. Agnello ,  Detlev A. Gruetzmacher ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

    IPC分类号： C30B25/02 ,  H01L21/205 ,  H01L21/203

    CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636

    摘要： A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system. Further, in order to achieve an optimal trade-off between the need for an inert ambience to promote silane reaction at low temperature and the need for a hydrogen ambience to prevent surface oxidation from inadvertant residual impurities, depositions are carried out in an ambience composed primarily of He but always containing some H.sub.2. Also, the relative deposition rates on a patterned surface of polycrystalline Si on insulator areas and single crystal Si on single crystal seed areas, when using the reactant silane, are dependent on the temperature of deposition and the relative concentrations of hydrogen and inert gas, e.g., helium, in the ambient gas, and can be controlled by regulating these parameters.

    摘要翻译： 通过使用APCVD工艺在低温下通过选择性或覆盖沉积在不完全清洁的Si表面上生长Si的低缺陷密度外延层的系统和方法，其中在表面上生长第一薄例如10nm的Si层， 硅烷或乙硅烷，然后在相同的低温（例如550℃至850℃）下从二氯硅烷（DCS）中生长剩余的膜。随后在第一层上用DCS生长第二层， 特别是如果在相同的沉积系统中立即进行，则不会引入额外的缺陷，并且可能与在硅烷系统中不可用的高且受控的n型掺杂相结合。 此外，为了在惰性气氛促进低温下的硅烷反应的需要和氢气氛的需要之间实现最佳的权衡，以防止表面氧化从不经意的残留杂质，沉积在主要组成的环境中进行 他总是含有一些H2。 此外，当使用反应物硅烷时，在单晶种子区域上的多晶Si绝缘体区域和单晶Si的图案化表面上的相对沉积速率取决于沉积温度和氢气和惰性气体的相对浓度，例如 ，氦气，在环境气体中，并且可以通过调节这些参数来控制。

    Semiconductor chip having both compact memory and high performance logic
    15.
    发明授权
    Semiconductor chip having both compact memory and high performance logic 有权
    具有紧凑型存储器和高性能逻辑的半导体芯片

    公开(公告)号：US06686617B2

    公开(公告)日：2004-02-03

    申请号：US09878804

    申请日：2001-06-11

    申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

    摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

    摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

    Vertical trench-formed dual-gate FET device structure and method for creation
    16.
    发明授权
    Vertical trench-formed dual-gate FET device structure and method for creation 失效
    垂直沟槽形双栅FET器件结构及其制作方法

    公开(公告)号：US06406962B1

    公开(公告)日：2002-06-18

    申请号：US09761931

    申请日：2001-01-17

    申请人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L21336

    CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642

    摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

    摘要翻译： 本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有 多个可选择的栅极长度。 本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。 具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点 由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。 附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。