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公开(公告)号：US08234606B2
公开(公告)日：2012-07-31
申请号：US13080716
申请日：2011-04-06
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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公开(公告)号：US20110185330A1
公开(公告)日：2011-07-28
申请号：US13080716
申请日：2011-04-06
IPC分类号： G06F17/50
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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公开(公告)号：US20100032809A1
公开(公告)日：2010-02-11
申请号：US12188234
申请日：2008-08-08
IPC分类号： H01L23/538 , H01L21/768 , G06F17/50
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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14.发明申请STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS 有权垂直双极晶体管性能改进的结构和方法公开(公告)号：US20060249813A1
公开(公告)日：2006-11-09
申请号：US10908361
申请日：2005-05-09
申请人： James Dunn , David Harame , Jeffrey Johnson , Alvin Joseph
发明人： James Dunn , David Harame , Jeffrey Johnson , Alvin Joseph
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L27/0823 , H01L29/66242
摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.
摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。
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公开(公告)号：US20060071292A1
公开(公告)日：2006-04-06
申请号：US10711744
申请日：2004-10-01
申请人： Douglas Coolbaugh , Ebenezer Eshun , Alvin Joseph , Robert Rassel
发明人： Douglas Coolbaugh , Ebenezer Eshun , Alvin Joseph , Robert Rassel
IPC分类号： H01L29/93 , H01L31/108
CPC分类号： H01L29/66143 , H01L29/0615 , H01L29/0692 , H01L29/872
摘要： Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.
摘要翻译： 肖特基势垒二极管使用介电分离区域结合活性区域。 电介质分离区允许在至少一个维度上消除保护环。 此外，在集成电路器件的有源部分中使用介质分离区可以通过消除该保护环来减少或消除寄生电容。
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公开(公告)号：US20070264787A1
公开(公告)日：2007-11-15
申请号：US11830376
申请日：2007-07-30
申请人： James Dunn , Alvin Joseph , Qizhi Liu
发明人： James Dunn , Alvin Joseph , Qizhi Liu
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.
摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。
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公开(公告)号：US20060060886A1
公开(公告)日：2006-03-23
申请号：US10711486
申请日：2004-09-21
申请人： James Dunn , Alvin Joseph , Qizhi Liu
发明人： James Dunn , Alvin Joseph , Qizhi Liu
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.
摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。
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公开(公告)号：US07968975B2
公开(公告)日：2011-06-28
申请号：US12188234
申请日：2008-08-08
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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19.发明申请LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权通过VIAS的低电阻和电感及其制造方法公开(公告)号：US20070190692A1
公开(公告)日：2007-08-16
申请号：US11275542
申请日：2006-01-13
申请人： Mete Erturk , Robert Groves , Jeffrey Johnson , Alvin Joseph , Qizhi Liu , Edmund Sprogis , Anthony Stamper
发明人： Mete Erturk , Robert Groves , Jeffrey Johnson , Alvin Joseph , Qizhi Liu , Edmund Sprogis , Anthony Stamper
IPC分类号： H01L21/50
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。
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20.发明申请BIPOLAR TRANSISTOR STRUCTURE WITH SELF-ALIGNED RAISED EXTRINSIC BASE AND METHODS 有权具有自对准基极的双极晶体管结构和方法公开(公告)号：US20060231924A1
公开(公告)日：2006-10-19
申请号：US11169444
申请日：2005-06-29
申请人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
发明人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
IPC分类号： H01L21/331 , H01L27/082 , H01L27/102 , H01L31/11
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译： 本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加 。 该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。 在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。 本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。 本发明还包括所得到的双极晶体管结构。
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