公开(公告)号：US08295087B2

公开(公告)日：2012-10-23

申请号：US12456354

申请日：2009-06-16

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C16/04 ,  G11C11/4193

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459

摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.

摘要翻译： 非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。 非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。 非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管 非易失性存储单元。 产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

公开(公告)号：US20090310411A1

公开(公告)日：2009-12-17

申请号：US12455936

申请日：2009-06-09

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C16/16 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

摘要翻译： 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

公开(公告)号：US20090279360A1

公开(公告)日：2009-11-12

申请号：US12387771

申请日：2009-05-07

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L21/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C2211/5641 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  Y10T29/41

摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR闪存非易失性存储器电路阵列。 每个NOR非易失性存储器电路包括以NAND串串联连接的多个电荷保持晶体管。 最高电荷保持晶体管的漏极连接到与串联连接的电荷保持晶体管相关联的位线，并且最下面的电荷保持晶体管的源极连接到与电荷保持晶体管相关联的源极线。 每行上的电荷保持晶体管的每个控制栅极共同连接到字线。 电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

公开(公告)号：US06262622B1

公开(公告)日：2001-07-17

申请号：US09479649

申请日：2000-01-08

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

IPC分类号： G05F302

CPC分类号： G05F3/242

摘要： A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

摘要翻译： 高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。 三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。 低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。 在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

公开(公告)号：US08345481B2

公开(公告)日：2013-01-01

申请号：US13317678

申请日：2011-10-25

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C2211/5641 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  Y10T29/41

摘要： A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

摘要翻译： NOR闪存非易失性存储器或可重构逻辑器件具有NOR闪存非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过 当电荷保持晶体管未被选择用于读取时的电荷保持晶体管。 最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。 电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

公开(公告)号：US08274829B2

公开(公告)日：2012-09-25

申请号：US12455936

申请日：2009-06-09

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34 ,  G11C11/4193

CPC分类号： G11C8/12 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

摘要翻译： 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

公开(公告)号：US6160737A

公开(公告)日：2000-12-12

申请号：US369761

申请日：1999-07-06

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

IPC分类号： G11C16/04 ,  G11C16/12 ,  G11C16/16

CPC分类号： G11C16/12 ,  G11C16/0416 ,  G11C16/16

摘要： Bias conditions for improving the efficiency of repairing, programming and erasing the threshold voltages of non-volatile memory devices. A positive voltage is applied to the source region of a non-volatile memory cell. The control gate of the memory cell is applied with another positive voltage higher the voltage at the source region. The difference between the two voltages is proportional to the desired final threshold voltage. The drain region can be applied with a positive voltage directly from the power supply of the memory device. A negative voltage is applied to the bulk of the memory device so that a large electric field across the control gate and the bulk can induce hot-electron injection. By selecting the proper voltage level at the control gate, the method can be used for the repair, program or erase operation of memory devices.

摘要翻译： 用于提高修复，编程和擦除非易失性存储器件的阈值电压效率的偏置条件。 正电压被施加到非易失性存储单元的源极区域。 存储单元的控制栅极被施加在源极区域上的电压更高的另一个正电压。 两个电压之间的差异与期望的最终阈值电压成比例。 漏极区域可以直接从存储器件的电源施加正电压。 负电压被施加到存储器件的大部分，使得跨越控制栅极和本体的大电场可以引起热电子注入。 通过在控制门选择适当的电压电平，该方法可用于存储器件的修复，编程或擦除操作。

公开(公告)号：US5978283A

公开(公告)日：1999-11-02

申请号：US109652

申请日：1998-07-02

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/14 ,  H02M3/07 ,  G11C7/00 ,  G05F3/16

CPC分类号： G11C16/12 ,  G11C16/14 ,  G11C5/145 ,  H02M3/073

摘要： Charge pump circuits for stepping up high voltages for flash memory array are disclosed. A first circuit comprises a plurality of series-coupled charge pumps having pump capacitors connected to each pump stage. A first group of charge pumps of the pump circuit are AC coupled through pump capacitors to two non-overlapping pulse trains. To reduce the high voltage that a pump capacitor has to withstand, each pump capacitor after the first group is connected to an earlier pump stage instead of the non-overlapping pulse trains. Therefore, the charge pump circuit can output voltage higher than the breakdown voltage of the pump capacitors. A second circuit comprising a configurable charge pump circuit is also presented. By connecting selected pump stages through diode paths to the output of the charge pump circuit and having a plurality of pulse train inputs, the charge pump circuit can be configured as a high voltage low current charge pump or a low voltage high current charge pump dependent on how pulse train signals are provided to the pulse train inputs. Finally, an improved structure for pump capacitors used in the charge pump circuit is presented.

摘要翻译： 公开了用于升高闪存阵列的高电压的电荷泵电路。 第一电路包括多个串联耦合的电荷泵，其具有连接到每个泵级的泵电容器。 泵电路的第一组电荷泵通过泵电容器交流耦合到两个不重叠的脉冲串。 为了降低泵电容器必须承受的高电压，第一组之后的每个泵浦电容器连接到较早的泵级而不是不重叠的脉冲串。 因此，电荷泵电路可以输出高于泵电容器的击穿电压的电压。 还提出了包括可配置电荷泵电路的第二电路。 通过将所选择的泵级通过二极管路连接到电荷泵电路的输出并具有多个脉冲串输入，电荷泵电路可被配置为高电压低电流电荷泵或低压大电流电荷泵，依赖于 如何将脉冲序列信号提供给脉冲串输入。 最后，介绍了在电荷泵电路中使用的泵浦电容器的改进结构。

公开(公告)号：US5953250A

公开(公告)日：1999-09-14

申请号：US159830

申请日：1998-09-24

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  H01L27/115 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3445 ,  H01L27/115 ,  G11C2211/5621 ,  G11C8/14

摘要： A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.

摘要翻译： 闪存电路包括具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器。 字线解码器和源极线解码器提供同时擦除闪存中两个相邻字线的存储单元的能力，并逐字地验证存储单元字。 通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。 解码架构提供了可能从一对到大量多对字线的灵活的擦除大小。 通过将字线的存储单元划分成多个段并具有由源段控制线和晶体管控制的分段源极线，解码电路还提供选择用于擦除的字线段的存储单元的能力。 对于源段控制线和晶体管以及字线的布局提出了几种不同的方法。

公开(公告)号：US5856942A

公开(公告)日：1999-01-05

申请号：US884926

申请日：1997-06-30

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  H01L27/115 ,  G11C11/34

CPC分类号： G11C16/3427 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3445 ,  H01L27/115 ,  G11C2211/5621 ,  G11C8/14

摘要： A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

摘要翻译： 具有具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器的闪存电路被公开。 字线解码器和源极线解码器提供同时擦除闪存中两个相邻字线的存储单元的能力，并逐字地验证存储单元字。 通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。 解码架构提供了可以从一对到大量多对字线的灵活的擦除大小。 通过将字线的存储单元划分成多个段，解码电路还提供选择用于擦除的字线段的存储单元的能力。