公开(公告)号：US20120132999A1

公开(公告)日：2012-05-31

申请号：US13303099

申请日：2011-11-22

申请人： Evelyne Gridelet ,  Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez

发明人： Evelyne Gridelet ,  Tony Vanhoucke ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Blandine Duriez

IPC分类号： H01L27/06 ,  H01L29/732 ,  H01L21/331

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0813 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/7322

摘要： Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

摘要翻译： 与示例实施例一致，存在制造双极晶体管的方法，其包括提供包括有源区的衬底; 沉积层叠; 在所述层叠层中的有源区上形成基窗; 在所述基窗中形成至少一个支柱，其中，所述支柱的一部分抵抗抛光; 在所得结构上沉积发射体材料，从而填充所述基窗; 并通过研磨平坦化沉积的发射体材料。 根据另一示例性实施例，可以根据上述方法制造双极晶体管。

公开(公告)号：US08871599B2

公开(公告)日：2014-10-28

申请号：US13599389

申请日：2012-08-30

申请人： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Blandine Duriez ,  Evelyne Gridelet ,  Hans Mertens ,  Tony Vanhoucke

发明人： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Blandine Duriez ,  Evelyne Gridelet ,  Hans Mertens ,  Tony Vanhoucke

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/737

CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66242

摘要： Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.

摘要翻译： 公开了一种集成电路和制造包括双极晶体管的集成电路的方法，所述方法包括提供包括由包括集电极的有源区域分离的一对隔离区域的衬底; 在所述衬底上形成基层堆叠; 形成具有第一迁移温度和蚀刻停止层的迁移层; 形成具有第二迁移温度的基底接触层; 蚀刻基底接触层中的发射器窗口，从而形成从发射器窗口延伸的空腔; 并在氢气氛中将所得结构暴露于第一迁移温度，由此用迁移层材料填充空腔。

公开(公告)号：US08101491B2

公开(公告)日：2012-01-24

申请号：US12912030

申请日：2010-10-26

申请人： Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Hans Mertens

发明人： Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Hans Mertens

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L29/66242

摘要： According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter.

摘要翻译： 根据示例性实施例，异质结双极晶体管HBT包括浅沟槽隔离，STI，与埋藏式集电极接触的掩埋集电极漂移区周围的结构。 沉积并蚀刻包括栅极氧化物和栅极的栅极堆叠，以在掩埋集电极漂移区域上限定基极窗并与STI结构重叠。 继续蚀刻处理以选择性地蚀刻STI结构之间的掩埋的集电极漂移区域以形成基底阱。 可选择性沉积SiGeC，以在基底阱中形成外延硅 - 锗，以与基底阱和基底窗的侧壁上的掩埋集电极漂移区和多晶硅 - 锗接触。 然后形成间隔物以及发射体。

公开(公告)号：US08173511B2

公开(公告)日：2012-05-08

申请号：US12094303

申请日：2006-10-29

申请人： Joost Melai ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers

发明人： Joost Melai ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/66287

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2） 和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体 （12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性 外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A） （7）连接到多晶半导体层（5），之后是间隔 （S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31） ）。 根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），其从突出部分观察到突出部分 底层半导体层（5）。 以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

公开(公告)号：US08963219B2

公开(公告)日：2015-02-24

申请号：US13270898

申请日：2011-10-11

申请人： Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

发明人： Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

IPC分类号： H01L29/66 ,  H01L29/76 ,  H01L21/337 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/10 ,  H01L29/165

CPC分类号： H01L29/7391 ,  B82Y10/00 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7613

摘要： A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

摘要翻译： 隧道场效应晶体管及其制造方法。 晶体管包括半导体衬底。 晶体管还包括位于衬底的主表面上的栅极。 晶体管还包括第一导电类型的漏极。 晶体管还包括在栅极下延伸的第二导电类型的源。 源极通过沟道区和栅极电介质与栅极分离。 晶体管可操作以允许电荷载流子从反型层通过源的上表面穿透。

公开(公告)号：US20120086058A1

公开(公告)日：2012-04-12

申请号：US13270898

申请日：2011-10-11

申请人： Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

发明人： Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7391 ,  B82Y10/00 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7613

摘要： A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

摘要翻译： 隧道场效应晶体管及其制造方法。 晶体管包括半导体衬底。 晶体管还包括位于衬底的主表面上的栅极。 晶体管还包括第一导电类型的漏极。 晶体管还包括在栅极下延伸的第二导电类型的源。 源极通过沟道区和栅极电介质与栅极分离。 晶体管可操作以允许电荷载流子从反型层通过源的上表面穿透。

公开(公告)号：US07074685B2

公开(公告)日：2006-07-11

申请号：US10515763

申请日：2003-05-27

申请人： Petrus Hubertus Cornelis Magnee ,  Johannes Josephus Theodorus Marinus Donkers

发明人： Petrus Hubertus Cornelis Magnee ,  Johannes Josephus Theodorus Marinus Donkers

IPC分类号： H01L21/331 ,  H01L21/36

CPC分类号： H01L29/66242

摘要： A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insulating layer. A transistor area opening is etched through the conductive layer, and an SiGe base layer is deposited inside the transistor area opening. An insulator is formed on an upper surface so as to fill the transistor area opening, wherein prior to filling the opening, a nitride layer is formed as an inner layer of the transistor area opening.

摘要翻译： 制造半导体器件的方法包括使用非选择性外延生长的SiGe（C）异质结双极晶体管，其中在衬底上形成绝缘层，并且在绝缘层上设置包括导电层的层结构。 通过导电层蚀刻晶体管区域开口，并且在晶体管区域开口内部沉积SiGe基极层。 在上表面上形成绝缘体以填充晶体管区域开口，其中在填充开口之前，形成氮化物层作为晶体管区域开口的内层。

公开(公告)号：US20090203214A1

公开(公告)日：2009-08-13

申请号：US12304332

申请日：2007-06-06

申请人： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers

发明人： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers

IPC分类号： H01L21/306

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (1), whereby in the semiconductor body (1) a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body (1), which is formed on the surface of the semiconductor device (10) as a nano wire (2), whereupon a layer (3) of a material is deposited over the semiconductor body (1) and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire (3) becomes exposed. According to the invention, a further layer (4) of a further material is deposited over the semiconductor body with the nano wire (2) before the layer (3) of the material is deposited, which further layer (4) is given a thickness smaller than the height of the nano wire (2), and a material is chosen for the further material such that, viewed in projection, the transition between the layer (3) and the further layer (4) is discernible before the nano wire (2) is reached. In this way the nano wire (2) can be exposed more accurately in the device (10). This increases the yield of useful devices (10).

摘要翻译： 本发明涉及一种制造具有基板（11）和半导体本体（1）的半导体器件（10）的方法，由此在半导体本体（1）中，通过台状突起形成半导体元件 形成在半导体器件（10）的表面上的半导体本体（1）作为纳米线（2），由此在半导体本体（1）上沉积材料层（3），并且得到的结构 随后在化学机械抛光工艺中平坦化，使得纳米线（3）的上侧暴露。 根据本发明，在材料的层（3）沉积之前，另外的材料层（4）在纳米线（2）之上沉积在半导体主体上方，该层（4）被赋予厚度 小于纳米线（2）的高度，并且为另外的材料选择材料，使得从投影中看，层（3）和另外的层（4）之间的过渡在纳米线（2） 2）到达。 以这种方式，可以在装置（10）中更准确地暴露纳米线（2）。 这增加了有用装置的产量（10）。

公开(公告)号：US20080237871A1

公开(公告)日：2008-10-02

申请号：US12093649

申请日：2006-10-27

申请人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

发明人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L21/76889 ,  H01L2221/1094

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体本体（12）设置有至少一个半导体元件（E）并且包括单晶硅（1）区域 通过在单晶硅区域（1）上提供金属硅化物区域（3）并且在金属硅化物区域（3）的顶部上提供低结晶度硅区域（4），在其上形成外延硅区域（2） 之后，通过加热将低结晶性硅区域（4）变换为具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度的底部移动 硅区域（4）到外延硅区域（2）的顶部。 根据本发明，金属硅化物区域（3）的水平形成有形成有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中， 并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），然后将外延硅 形成区域（2）。 以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准的方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

公开(公告)号：US08114774B2

公开(公告)日：2012-02-14

申请号：US12304332

申请日：2007-06-06

申请人： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers

发明人： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers

IPC分类号： H01L21/302

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

摘要： The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body, whereby in the semiconductor body a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body, which is formed on the surface of the semiconductor device as a nano wire, whereupon a layer of a material is deposited over the semiconductor body and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire becomes exposed. According to the invention, a further layer of a further material is deposited over the semiconductor body with the nano wire before the layer of the material is deposited, which further layer is given a thickness smaller than the height of the nano wire, and a material is chosen for the further material such that, viewed in projection, the transition between the layer and the further layer is discernible before the nano wire is reached. In this way the nano wire can be exposed more accurately in the device. This increases the yield of useful devices.

摘要翻译： 本发明涉及一种制造具有衬底和半导体本体的半导体器件的方法，由此在半导体本体中，半导体元件通过形成在半导体本体的表面上的半导体本体的台面状突起形成 半导体器件作为纳米线，由此在半导体本体上沉积材料层，并且随后在化学机械抛光工艺中使所得结构平坦化，使得纳米线的上侧暴露。 根据本发明，在沉积材料层之前，在纳米线之前，在半导体主体上沉积另外一层另外的材料，该另一层的厚度小于纳米线的高度，并且材料 被选择用于进一步的材料，使得从投影中观察到，在达到纳米线之前，层与另外的层之间的转变是可辨别的。 以这种方式，可以在器件中更准确地暴露纳米线。 这增加了有用装置的产量。