利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.024 秒)

    Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method
    1.
    发明申请
    Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method 审中-公开
    制造使用这种方法获得的半导体器件和半导体器件的方法

    公开(公告)号：US20080237871A1

    公开(公告)日：2008-10-02

    申请号：US12093649

    申请日：2006-10-27

    申请人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

    发明人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

    IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L23/532

    CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L21/76889 ,  H01L2221/1094

    摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.

    摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体本体（12）设置有至少一个半导体元件（E）并且包括单晶硅（1）区域 通过在单晶硅区域（1）上提供金属硅化物区域（3）并且在金属硅化物区域（3）的顶部上提供低结晶度硅区域（4），在其上形成外延硅区域（2） 之后，通过加热将低结晶性硅区域（4）变换为具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度的底部移动 硅区域（4）到外延硅区域（2）的顶部。 根据本发明，金属硅化物区域（3）的水平形成有形成有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中， 并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），然后将外延硅 形成区域（2）。 以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准的方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20110018065A1

    公开(公告)日：2011-01-27

    申请号：US12918398

    申请日：2009-02-17

    申请人： Gilberto Curatola ,  Prabhat Agarwal ,  Mark J. H. Van Dal ,  Vijayaraghavan Madakasira

    发明人： Gilberto Curatola ,  Prabhat Agarwal ,  Mark J. H. Van Dal ,  Vijayaraghavan Madakasira

    IPC分类号： H01L29/775 ,  H01L27/088 ,  H01L21/336

    CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775

    摘要： A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20′) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20′); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20′ may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.

    摘要翻译： 公开了一种制造半导体器件的方法，其包括提供绝缘载体（10），例如氧化物晶片; 在所述载体（10）上的源极结构（12）和漏极结构（14）之间提供沟道结构（20）; 选择性地去除所述通道结构（20）的一部分，从而在所述通道结构（20）和所述载体（10）之间形成凹部（22）。 将所述装置暴露于退火步骤，使得所述通道结构（20'）获得基本上圆柱形的形状; 形成围绕所述基本上圆柱形的通道结构（20'）的约束层（40）; 生长围绕限制层（40）的氧化物层（50）; 以及形成围绕所述氧化物层（50）的栅极结构（60）。 基本上圆柱形的沟道结构20'可以包括半导体层30.还公开了相应的半导体器件。

    Nanowire tunneling transistor
    4.
    发明授权
    Nanowire tunneling transistor 失效
    纳米线隧道晶体管

    公开(公告)号：US07791108B2

    公开(公告)日：2010-09-07

    申请号：US12161574

    申请日：2007-01-24

    申请人： Fred Hurkx ,  Prabhat Agarwal

    发明人： Fred Hurkx ,  Prabhat Agarwal

    IPC分类号： H01L21/336 ,  H01L21/8235

    CPC分类号： H01L29/1054 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S977/75 ,  Y10S977/813 ,  Y10S977/938

    摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

    摘要翻译： 晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。 在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。 在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

    Circuit and method to convert a single ended signal to duplicated signals
    5.
    发明授权
    Circuit and method to convert a single ended signal to duplicated signals 有权
    将单端信号转换为重复信号的电路和方法

    公开(公告)号：US07538593B2

    公开(公告)日：2009-05-26

    申请号：US11710270

    申请日：2007-02-23

    申请人： Prabhat Agarwal ,  Mayank Goel ,  Pradip Mandal

    发明人： Prabhat Agarwal ,  Mayank Goel ,  Pradip Mandal

    IPC分类号： G06F1/04

    CPC分类号： H03K5/151

    摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.

    摘要翻译： 公开了将单端信号转换为差分信号的电路。 该电路具有两条路径，其中两条路径中的每条路径包括多个级。 两个路径中的每个路段的数量是相同的。 两个路径的第一路径包括缓冲段和至少一个逆变器级。 两路径的第二路径包括至少两个逆变器级。 缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。 缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

    NANOWIRE TUNNELING TRANSISTOR
    6.
    发明申请
    NANOWIRE TUNNELING TRANSISTOR 失效
    NANOWIRE隧道晶体管

    公开(公告)号：US20090008631A1

    公开(公告)日：2009-01-08

    申请号：US12161574

    申请日：2007-01-24

    申请人： Godefridus Andrianus Maria Hurkx ,  Prabhat Agarwal

    发明人： Godefridus Andrianus Maria Hurkx ,  Prabhat Agarwal

    IPC分类号： H01L29/06

    CPC分类号： H01L29/1054 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S977/75 ,  Y10S977/813 ,  Y10S977/938

    摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

    摘要翻译： 晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。 在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。 在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

    GEIGER MODE AVALANCHE PHOTODIODE
    7.
    发明申请
    GEIGER MODE AVALANCHE PHOTODIODE 有权

    公开(公告)号：US20090008566A1

    公开(公告)日：2009-01-08

    申请号：US12162999

    申请日：2007-01-17

    申请人： Prabhat Agarwal ,  Jan Sonsky ,  Lasse Juhana Kauppinen

    发明人： Prabhat Agarwal ,  Jan Sonsky ,  Lasse Juhana Kauppinen

    IPC分类号： G01T1/24 ,  H01L31/107 ,  H01L31/18

    CPC分类号： H01L27/14658 ,  H01L27/1464 ,  H01L27/14683 ,  H01L31/107

    摘要： A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).

    摘要翻译： 使用绝缘体上硅晶片和衬底转移工艺制造雪崩模式光电二极管阵列（102）。 阵列包括多个光电二极管（100）。 光电二极管（100）包括电绝缘层（206），耗尽区（204）以及第一（208）和第二（210）掺杂区。 互连层（212）包括提供到光电二极管的电连接的电极（214,216）。 光电二极管阵列（102）由处理晶片（217）承载。

    Implementation of avalanche photo diodes in (Bi)CMOS processes
    10.
    发明授权
    Implementation of avalanche photo diodes in (Bi)CMOS processes 有权
    （Bi）CMOS工艺中雪崩光电二极管的实现

    公开(公告)号：US07759650B2

    公开(公告)日：2010-07-20

    申请号：US12298206

    申请日：2007-04-10

    申请人： Anco Heringa ,  Thomas Frach ,  Prabhat Agarwal

    发明人： Anco Heringa ,  Thomas Frach ,  Prabhat Agarwal

    IPC分类号： G01T1/24

    CPC分类号： H01L31/115 ,  H01L27/1446 ,  H01L31/107 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    摘要： A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n-doped region (16) disposed adjacent to the substrate (14), and a p-doped region (18) disposed adjacent to the n-doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p-doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p-doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n-doped region.

    摘要翻译： 辐射检测器（46）包括形成在衬底（14）上的半导体层（12）和形成在半导体层（12）上的闪烁体（30）。 半导体层（12）包括邻近衬底（14）设置的n掺杂区域（16）和邻近于n掺杂区域（16）设置的p掺杂区域（18）。 沟槽（20）形成在半导体层（12）内并且围绕p掺杂区域（18）并且填充有减小pn结边缘处的pn结曲率的材料（22），其中 减少边缘的破坏。 闪烁体（30）设置在p掺杂区域（18）上并且光耦合到p掺杂区域（18）。 辐射检测器（46）还包括与n掺杂区域电接触的至少一个导电电极（24）。