摘要:
A method for vertically grounding and leading down form an outer side of a composite pole tower and pole tower thereof, wherein the method includes the following steps: extending an upper metal cross arm from an extended line of at least one side of a ground wire cross arm, vertically leading down a ground down-leading wire from a distal end of the upper metal cross arm, connecting the ground down-leading wire to the pole tower via a lower metal cross arm at a distance under a lower lead, and grounding the ground down-leading wire along a tower body of the pole tower, wherein when an lower portion of the tower body is a metal pipe, the ground down-leading wire is selectively directly connected to the metal pipe via the lower metal cross arm. The method facilitates in compressing the width of the transmission corridor to a maximum extent as well as designing a lightning protection, preventing the ground down-leading wire from short-circuiting with the tower body, and realizing the insulation function of the composite material tower body. The manner of using unilateral ground down-leading wire saves material, and is economical and simple in structure.
摘要:
A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.
摘要:
Methods and apparatus are provided for rotor and stator temperature compensation for field weakening current. The method comprises generating a phase voltage feed back signal Vph based in part on pre-defined optimal current commands (ID* and IQ*) received by the IPM, generating a phase voltage command (Vphcmd) based in part on a temperature of a magnetic rotor and stator of the IPM, and generating a phase voltage error (Verror) by subtracting the phase voltage feed back signal (Vph) from the phase voltage command (Vphcmd). The method further comprises generating a d-axis command current correction value (ΔId) and a q-axis command current correction value (ΔIq) from the phase voltage error (Verror); and adjusting the pre-defined optimal current commands (ID* and IQ*) by the d-axis and the q-axis command current correction values (ΔId and ΔIq).
摘要:
Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity.
摘要:
The techniques of the disclosure are directed to reducing power consumption in a device through adaptive backlight level (ABL) scaling. The techniques may utilize a temporal approach in implementing the ABL scaling to adjust the backlight level of a display for a current video frame in a sequence of video frames presented on the display. The techniques may include receiving an initial backlight level adjustment for the current video frame and determining whether to adjust the backlight level adjustment for the current video frame based on a historical trend. The techniques may also determine the historical trend of backlight level adjustments between the current video frame and one or more preceding video frames in the sequence.
摘要:
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
摘要:
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.
摘要:
A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.
摘要:
A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.
摘要:
A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.