公开(公告)号：US09029959B2

公开(公告)日：2015-05-12

申请号：US13537101

申请日：2012-06-29

申请人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

发明人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

IPC分类号： H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L21/02321 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517

摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

公开(公告)号：US20140001570A1

公开(公告)日：2014-01-02

申请号：US13537101

申请日：2012-06-29

申请人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

发明人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

IPC分类号： H01L27/088 ,  H01L21/31

CPC分类号： H01L21/02321 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517

摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

公开(公告)号：US20130330843A1

公开(公告)日：2013-12-12

申请号：US13490740

申请日：2012-06-07

申请人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28202 ,  H01L22/12 ,  H01L22/26 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

公开(公告)号：US20120329230A1

公开(公告)日：2012-12-27

申请号：US13164891

申请日：2011-06-21

申请人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

发明人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28211 ,  H01L21/28238

摘要： A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.

摘要翻译： 一种制造含硅氧化物层的方法，包括在半导体衬底的表面上提供化学氧化物层，在1000℃或更高的温度下在无氧环境中除去化学氧化物层，以提供裸露 在半导体衬底的表面上，以1000℃的温度将半导体衬底的裸露表面的含氧气体首次引入半导体衬底的裸露表面。然后在第二时间内将温度降至室温 同时保持含氧气体的流速，从而提供厚度范围从0.5到10的含硅氧化物层。

公开(公告)号：US08492290B2

公开(公告)日：2013-07-23

申请号：US13164891

申请日：2011-06-21

申请人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Jinping Liu

发明人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Jinping Liu

IPC分类号： H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28211 ,  H01L21/28238

摘要： A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.

摘要翻译： 一种制造含硅氧化物层的方法，包括在半导体衬底的表面上提供化学氧化物层，在1000℃或更高的温度下在无氧环境中除去化学氧化物层，以提供裸露 在半导体衬底的表面上，以1000℃的温度将半导体衬底的裸露表面的含氧气体首次引入半导体衬底的裸露表面。然后在第二时间内将温度降至室温 同时保持含氧气体的流速，从而提供厚度范围从0.5到10的含硅氧化物层。

公开(公告)号：US09099461B2

公开(公告)日：2015-08-04

申请号：US13490740

申请日：2012-06-07

申请人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui

IPC分类号： H01L21/66 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28202 ,  H01L22/12 ,  H01L22/26 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

公开(公告)号：US08809152B2

公开(公告)日：2014-08-19

申请号：US13300146

申请日：2011-11-18

申请人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

发明人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

摘要翻译： 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。

公开(公告)号：US20130126986A1

公开(公告)日：2013-05-23

申请号：US13300146

申请日：2011-11-18

申请人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

发明人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

摘要翻译： 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。

公开(公告)号：US20140001575A1

公开(公告)日：2014-01-02

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

摘要翻译： 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

公开(公告)号：US08941177B2

公开(公告)日：2015-01-27

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L29/36 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.